mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 50

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

13. Interrupt
There are 12 interrupt sources available in MG84FL54B. Each interrupt source can be individually enabled or
disabled by setting or clearing an enable bit in the Interrupt Enable registers (IE, AUXIE and XICON). There is
also a global disable bit (EA) in the IE register, which can be cleared to disable all interrupts at once. Fig 13-1
shows the interrupt structure in MG84FL54B.
Each interrupt source has a corresponding bit in the Interrupt Priority registers (IP and AUXIP) to represent its
priority. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two interrupt requests
of different priority levels are received simultaneously, the request of higher priority is serviced. If interrupt
requests of the same priority level are received simultaneously, an internal polling sequence determine which
request is serviced. The two priority level interrupt structure allows great flexibility in controlling the handling of
these interrupt sources. The following Table 13-1 shows the internal polling sequence in the same priority level
and the interrupt vector address.
13.1. Interrupt Source
Table 13-1 Interrupt Sources
Note:
The external interrupt /INT0 and /INT1 can each be either level-activated or transition-activated, depending on
bits IT0 and IT1 in register TCON. The external interrupt /INT2 and /INT3 can be programmed high/low level-
activated or rising/falling edge-activated depending on bits ILx and ITx (x=2 or 3) in register XICON. The flags
that actually generate these interrupts are bits IE0 and IE1 in TCON, IE2 and IE3 in XICON. When an external
interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored
to only if the interrupt was transition –activated, then the external requesting source is what controls the request
flag, rather than the on-chip
50
Source
No.
#10
#11
#12
#13
#14
#15
#16
#1
#2
#3
#4
#5
#6
#7
#8
#9
The USB interrupt flags include: (See
(1) URST, URSM and USUS: contained in USB register UPCON.
(2) UTXD0, URXD0, UTXD1, UTXD2, ASOFIF and SOFIF: contained in USB register UIFLG.
(3) UTXD3, URXD3: contained in USB register UIFLG1
Two Wire Serial Interface
External Interrupt, INT2*
External Interrupt, INT3*
External Interrupt, INT0
External Interrupt, INT1
Keypad Interrupt
Serial Port
Interrupt
Timer 0
Timer 1
Timer 2
Name
USB
SPI
-
-
-
-
hardware.
Interrupt
Enable
ETWSI
EUSB
MG84FL54B Data Sheet
ESPI
EKBI
EX0
ET0
EX1
ET1
ET2
EX2
EX3
Bit
ES
-
-
-
-
19.3 USB
TF2+ EXF2
(See Note)
Interrupt
RI+TI
SPIF
KBIF
Interrupt)
Flag
TF0
TF1
IE0
IE1
IE2
IE3
Bit
SI
-
-
-
-
Interrupt
Priority
PTWSI
PUSB
PSPI
PKBI
Bits
PX0
PX1
PX2
PX3
PT0
PT1
PT2
PS
-
-
-
-
(Highest)
(Lowest)
Priority
Polling
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Address
Vector
000BH
001BH
002BH
003BH
004BH
005BH
006BH
007BH
0003H
0013H
0023H
0033H
0043H
0053H
0063H
0073H
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