mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 69

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

16.4. SPI Register
The following special function registers are related to the SPI operation:
SPCTL (Address=85H, SPI Control Register)
SSIG: /SS is ignored
If SSIG=1, MSTR decides whether the device is a master or slave.
If SSIG=0, the /SS pin decides whether the device is a master or slave.
SPEN: SPI enable
If SPEN=1, the SPI is enabled.
If SPEN=0, the SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
DORD: SPI data order
1: The LSB of the data byte is transmitted first.
0: The MSB of the data byte is transmitted first.
MSTR: Master/Slave mode select
CPOL: SPI clock polarity select
1: SPICLK is high when idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising
edge.
0: SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling
edge.
CPHA: SPI clock phase select
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is sampled on
the leading edge of SPICLK.
Note:
SPR1-SPR0: SPI clock rate select (associated with SPR2, when in master mode)
SPSTAT (Address=84H, SPI Status Register)
SPIF: SPI transfer completion flag
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If /SS
pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the “mode change”.
The SPIF is cleared in firmware by writing ‘1’ to this bit.
THRE (read-only): Transmit Holding Register (THR) Empty flag.
0: This bit is cleared by hardware when the THR is empty. That means the data in THR is loaded (by H/W) into
the Output Shift Register to be transmitted, and now the user can write the next data byte to SPDAT for next
transmission.
1: This bit is set by hardware just when SPDAT is written by firmware.
SPR2: SPI clock rate select (associated with SPR1 and SPR0)
SPDAT (Address=86H, SPI Data Register)
MEGAWIN
SSIG
SPIF
7
If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.
7
7
{SPR2,SPR1,SPR0} = 000: SYSCLK/4
SPEN
THRE
6
6
6
DORD
5
5
5
-
001: SYSCLK/6
010: SYSCLK/8
011: SYSCLK/12
MSTR
4
4
4
-
MG84FL54B Data sheet
100: SYSCLK/16
101: SYSCLK/24
110: SYSCLK/48
111: SYSCLK/96
CPOL
3
3
3
-
CPHA
2
2
2
-
SPR1
1
1
1
-
SPR0
SPR2
0
0
0
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