mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 52

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

13.2. Interrupt Structure
Fig 13-1 Interrupt Structure
13.3. How Interrupts are Handled
The interrupt flags are sampled every instruction cycle. The samples are polled during the following instruction
cycle. If one of the interrupt flags was in a set condition in the preceding cycle, the polling cycle will find it and
the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-
generated LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to the registers associated the interrupts.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3
52
/INT2
/INT3
XICON.IL2
XICON.IL3
USB interrupts
SPSTAT.SPIF
T2CON.EXF2
KBCON.KBIF
T2CON.TF2
TCON.TF0
TCON.TF1
SICON.SI
SCON.RI
SCON.TI
/INT0
/INT1
0
1
0
1
XICON.IT2
XICON.IT3
TCON.IT0
TCON.IT1
AUXIE.ETWSI
AUXIE.ESPI
AUXIE.EKBI
AUXIE.EUSB
MG84FL54B Data Sheet
IE2
IE3
IE0
IE1
XICON.EX2
XICON.EX3
Global Enable
IE.EX0
IE.ET0
IE.EX1
IE.ET1
IE.ES
IE.ET2
(IE.EA)
IPL,IPH,XICON
Registers
Highest Priority Level
Lowest Priority
Level Interrupt
Interrupt
Interrupt Polling
Sequence
MEGAWIN