mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 72

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

17.1. The Special Function Registers for TWSI
The Serial Interface Address Register, SIADR, Address=D1H
The CPU can read from and write to this register directly. SIADR is not affected by the TWSI hardware. The
contents of this register are irrelevant when TWSI is in a master mode. In the slave mode, the seven most
significant bits must be loaded with the microcontroller’s own slave address, and, if the least significant bit (GC)
is set, the general call address (00H) is recognized; otherwise it is ignored. The most significant bit corresponds
to the first bit received from the TWSI bus after a START condition.
SIADR (Address=D1H, TWSI Address Register)
The Serial Interface Data Register, SIDAT, Address=D2H
This register contains a byte of serial data to be transmitted or a byte which has just been received. The CPU
can read from or write to this register directly while it is not in the process of shifting a byte. This occurs when
TWSI is in a defined state and the serial interrupt flag (SI) is set. Data in SIDAT remains stable as long as SI is
set. While data is being shifted out, data on the bus is simultaneously being shifted in; SIDAT always contains
the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter
to slave receiver is made with the correct data in SIDAT.
SIDAT (Address=D2H, TWSI Data Register)
SIDAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an
acknowledge bit. The ACK flag is controlled by the TWSI hardware and cannot be accessed by the CPU. Serial
data is shifted through the ACK flag into SIDAT on the rising edges of serial clock pulses on the SCL line. When
a byte has been shifted into SIDAT, the serial data is available in SIDAT, and the acknowledge bit is returned by
the control logic during the 9th clock pulse. Serial data is shifted out from SIDAT on the falling edges of clock
pulses on the SCL line.
When the CPU writes to SIDAT, the bit SD7 is the first bit to be transmitted to the SDA line. After nine serial
clock pulses, the eight bits in SIDAT will have been transmitted to the SDA line, and the acknowledge bit will be
present in the ACK flag. Note that the eight transmitted bits are shifted back into SIDAT.
The Serial Interface Control Register, SICON, Address=F8H
The CPU can read from and write to this register directly. Two bits are affected by the TWSI hardware: the SI bit
is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the
bus. The STO bit is also cleared when ENS1="0".
SICON (Address=F8H, TWSI Control Register)
ENSI, the TWSI Hardware Enable Bit
When ENSI is "0", the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are
ignored, TWSI is in the not-addressed slave state, and STO bit in SICON is forced to "0". No other bits are
affected, and, P2.1 (SDA) and P2.0 (SCL) may be used as open drain I/O pins. When ENSI is "1", TWSI is
enabled, and, the P2.1 and P2.0 port latches must be set to logic 1 for the following serial communication.
72
|<----------------------------------------------- Own Slave Address ------------------------------------------------->|
<---------------------------------------------------- Shift direction ---------------------------------------------------->
CR2
(A6)
(D7)
7
7
7
ENSI
(A5)
(D6)
6
6
6
(D5)
STA
(A4)
5
5
5
MG84FL54B Data Sheet
STO
(A3)
(D4)
4
4
4
(A2)
(D3)
SI
3
3
3
(D2)
(A1)
AA
2
2
2
(A0)
(D1)
CR1
1
1
1
CR0
(D0)
GC
0
0
0
MEGAWIN