mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 23

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

[XCKS4~XCKS0] = OSCin – 1, where OSCin=1~25MHz.
For examples,
(1) If OSCin=12MHz, then fill [XCKS4~XCKS0] with 11, i.e., 01011B.
(2) If OSCin=6MHz, then fill [XCKS4~XCKS0] with 5, i.e., 00101B.
CKS2~CKS0: System clock divider selector, as follows table.
CKS2 CKS1 CKS0
CKCON2 (Address=BFH, Clock Control Register 2)
OSCDR0: On-chip XTAL oscillating driving control bits.
When this bit is clear, the driving of crystal oscillator is enough for oscillation up to 25MHz.
When this bit is set, the driving of crystal oscillator is enough for oscillation up to 16MHz.
EN_PLL: PLL enable bit.
1: Enable PLL.
0: Disable PLL.
PLL_RDY: PLL Ready flag.
It is a read only flag to indicate the PLL status on ready or not.
CK_SEL: System clock divider input select bit.
1: CLKin=48MHz.
0: CLKin=OSCin.
In the default state, the reset value of CKCON is 0x00 (CK_SEL=0, and CKS[2:0]=000B), so the system clock
(SYSCLK) comes from OSCin. The user can modify CKCON at any time to get a new system clock, which will
be active just after the modifying is completed.
In the applications which don’t care the frequency of system clock, the user can fill CKS2~CKS0 bits with a non-
zero value to slow the system clock before entering idle mode to get power saving.
MEGAWIN
0
0
0
1
1
1
1
0
7
-
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
-
OSCDR0
SYSCLK (System Clock)
5
CLKin
CLKin /2
CLKin /4
CLKin /8
CLKin /16
CLKin /32
CLKin /64
CLKin /128
default
4
-
MG84FL54B Data sheet
EN_USB
3
EN_PLL
2
PLL_RDY
1
CK_SEL
0
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