tm1300 NXP Semiconductors, tm1300 Datasheet - Page 108

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
90 MHz. The PLL is enabled and programmed as de-
scribed in
DDS clock rate is set by the VO_CLOCK.FREQUENCY
field according to the equation shown in
VO_CLK frequency can be a divider or multiplier of f
as determined by the PLL subsystem settings.
Low-jitter clock mode is automatically entered whenever
FREQUENCY[31] = 1. If FREQUENCY[31] = 0, the DDS
operates at 1/3 the rate (for compatibility with TM1000
code), and FREQUENCY must be set as shown in
Figure
7.8
The EVO emits a serial byte-data stream used by
CCIR 656 devices to generate a displayed image.
Figure 7-8
laced image. The field and line numbers are shown for
reference.
Interlaced images are generated by the display hardware
by controlling the vertical retrace timing. For reference,
7-4
Figure 7-6. DDS low-jitter oscillator frequency.
Figure 7-7. DDS slow speed oscillator frequency
Figure 7-8. Interlaced display: 525-line, 60-Hz image.
FREQUENCY
7-7.
IMAGE TIMING
Section
FREQUENCY
shows an NTSC-compatible, 525-line inter-
Field 1
Line 262
Line 263
Line 20
Line 21
7.18.
=
2
31
PRODUCT SPECIFICATION
=
+
------------------------------ -
9 f
------------------------------ -
3 f
f
f
DDS
DDS
DSPCPU
DSPCPU
2
2
Figure
32
32
7-6. The
DDS
Displayed Image
,
Scan Direction
Figure 7-9
interlaced frame timing illustrating the analog vertical re-
trace signal. The vertical retrace signal for the second
field begins in the middle of the horizontal line that ends
the first field. This causes the first line of the second field
to begin halfway across the display screen and the lines
of the second field to be scanned between the lines of
the first field, resulting in an interlaced display.
The analog timing required to generate the interlaced
signal is supplied by the display device. The CCIR 656
digital video signals generated by the EVO use frame
synchronization timing and do not generate any vertical
retrace timing.
7.8.1
The EVO generates pixels according to CCIR 656 timing
in YUV 4:2:2 co-sited format and outputs these pixels as
shown in
two, with four bytes per two pixels. Each pair of pixels
has two luminance bytes (Y0, Y1) and one pair of
chrominance bytes (U0, V0) arranged in the sequence
shown. The chrominance samples U0 and V0 are sam-
pled spatially co-sited with luminance sample Y0. For
PAL or NTSC video, pixels are generated at a nominal
rate of 13.5 Mpix/sec (27 MB/sec). Pixels are clocked out
on the positive edge of VO_CLK.
7.8.2
The CCIR 656 line timing is shown in
line begins with an EAV code, a blanking interval and an
SAV code, followed by the line of active video. The EAV
code indicates end of active video for the previous line,
and the SAV code indicates start of active video for the
current line.
Figure
CCIR 656 Pixel Timing
CCIR 656 Line Timing
shows a timing diagram of NTSC-compatible
7-10. Pixels are generated in groups of
Philips Semiconductors
Field 2
Line 282
Line 283
Line 524
Line 525
Figure
7-11. Each