tm1300 NXP Semiconductors, tm1300 Datasheet - Page 47

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2.4
The key to understanding TM1300 operation is observ-
ing that the DSPCPU and peripherals are time-shared
and that communication between units is through
SDRAM memory. The DSPCPU switches from one task
to the next; first it decompresses a video frame, then it
decompresses a slice of the audio stream, then back to
video, etc. As necessary, the DSPCPU issues com-
mands to the peripheral function units to orchestrate their
operation.
The DSPCPU can enlist the ICP and other coprocessors
to help with some of the straightforward, tedious tasks
associated with video processing. The ICP is very well
suited for arbitrary size horizontal and vertical video re-
sizing and color space conversion.
The DSPCPU can enlist the input/output peripherals to
autonomously receive or transmit digital video and audio
data with minimal CPU supervision. The I/O units have
been designed to interface to the outside world through
industry standard audio and video interfaces, while deliv-
ering or taking data in memory in formats suitable for
software processing.
2.4.1
An example TM-1300 implementation is as a video-de-
compression engine on a PCI card in a PC. In this case,
the PC does not need to know the TM1300 has a power-
ful, general-purpose CPU; rather, the PC just treats the
hardware on the PCI card as a ‘black-box’ engine.
Video decompression begins when the PC operating
system hands the TM1300 a pointer to compressed vid-
eo data in the PC’s memory (the details of the communi-
cation protocol are handled by the software driver in-
stalled in the PC’s operating system).
The DSPCPU fetches data from the compressed video
stream via the PCI bus, decompresses frames from the
video stream, and places them into local SDRAM. De-
compression may be aided by the VLD (variable-length
decoder) coprocessor unit, which implements Huffman
decoding and is controlled by the DSPCPU.
When a frame is ready for display, the DSPCPU gives
the ICP a display command. The ICP then autonomously
fetches the decompressed frame data from SDRAM and
transfers it over the PCI bus to the frame buffer in the
PC’s video display card. Alternately, video can be sent to
the graphics card using the VO unit.
2.4.2
Another typical application for TM1300 is in video com-
pression. In this case, uncompressed video is usually
supplied directly to the TM1300 system via the Video In
(VI) unit. A camera chip connected directly to the VI unit
supplies YUV data in 8-bit, 4:2:2 format. The VI unit sam-
ples the data from the camera chip and demultiplexes
the raw video to SDRAM in three separate areas, one
each for Y, U, and V.
When a complete video frame has been read from the
camera chip by the VI unit, it interrupts the DSPCPU.
BRIEF EXAMPLES OF OPERATION
Video Decompression in a PC
Video Compression
The DSPCPU compresses the video data in software
(using a set of powerful data-parallel multimedia opera-
tions) and writes the compressed data to a separate area
of SDRAM.
The compressed video data can now be transmitted or
stored in any of several ways. It can be sent to a host
system over the PCI bus for archival on local mass stor-
age, or the host can transfer the compressed video over
a network. The data can also be sent to a remote system
using the modem/ISDN interface to create, for example,
a video phone or videoconferencing system.
Since the powerful, general-purpose DSPCPU is avail-
able, the compressed data can be encrypted before be-
ing transferred for security.
2.5
The remainder of this chapter provides a brief introduc-
tion to the internal components of TM1300.
2.5.1
The internal bus (or data highway) connects all internal
blocks together and provides access to internal control/
status registers of each block, external SDRAM, and the
external bus peripheral chips. The internal bus consists
of separate 32-bit data and address buses. Transactions
on the bus use a block-transfer protocol. On-chip periph-
eral units and coprocessors can be masters or slaves on
the bus.
Access to the internal bus is controlled by a central arbi-
ter, which has a request line from each potential bus
master. The arbiter is programmable so that the arbitra-
tion algorithm can be tailored for different applications.
Peripheral units make requests to the arbiter for bus ac-
cess and, depending on the arbitration mode, bus band-
width is allocated to the units in different amounts. Each
mode allocates bandwidth differently, but each mode
guarantees each unit a minimum bandwidth and maxi-
mum service latency. All unused bandwidth is allocated
to the DSPCPU.
The bus allocation mechanism is one of the features of
TM1300 that makes it a true real-time system instead of
just a highly integrated microprocessor with unusual pe-
ripherals.
2.5.2
The heart of TM1300 is a powerful 32-bit DSPCPU core.
The DSPCPU implements a 32-bit linear address space
and 128, fully general-purpose 32-bit registers. The reg-
isters are not separated into banks; any operation can
use any register for any operand.
The TM1300 core uses a VLIW instruction-set architec-
ture and is fully general-purpose. The VLIW instruction
length allows five simultaneous operations to be issued
every clock cycle. These operations can target any five
of the 27 functional units in the DSPCPU, including inte-
ger and floating-point arithmetic units and data-parallel
multimedia operation units.
PRODUCT SPECIFICATION
INTRODUCTION TO TM1300 BLOCKS
Internal ‘Data Highway’ Bus
VLIW Processor Core
Overview
2-3