tm1300 NXP Semiconductors, tm1300 Datasheet - Page 171

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
is decremented, and this sequence repeats until TL
reaches ‘0’.
At the end of the PCI
interface will generate a DSPCPU interrupt if the appro-
priate IntE bit is set in BIU_CTL. Alternatively, DSPCPU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
During an SDRAM
face drives the address from SRC_ADR to the SDRAM
controller. The returned data is buffered in w_buffer. The
PCI interface then drives the address from DEST_ADR
and the data from w_buffer to the PCI bus. SRC_ADR
and DEST_ADR are incremented, the TL field in
DMA_CTL is decremented, and this sequence repeats
until TL reaches ‘0’.
At the end of the SDRAM
interface can generate a DSPCPU interrupt if the appro-
priate IntE bit is set in BIU_CTL. Alternatively, DSPCPU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
11.7.17 INT_CTL Register
The INT_CTL register contains three fields for setting,
enabling, and sensing the four PCI interrupt lines.
Table 11-19
INT_CTL.
INT (Interrupt bits). The INT field (bits 0..3 of INT_CTL)
can force a PCI interrupt to be signalled.
IE (Interrupt enable). The IE field (bits 4..7 of INT_CTL)
enables TM1300 to drive PCI interrupt lines.
IS (Interrupt state). The IS field (bits 8..11 of INT_CTL)
senses the state of the PCI interrupt lines.
Table 11-19. INT_CTL Bits
Figure 11-9
used to implement the control of each intx# pin.
See also
Field
INT
INT_CTL
IE
IS
Section 3.6, “TM1300 to Host Interrupts.”
Bit
10
11
0
1
2
3
4
5
6
7
8
9
shows a conceptual realization of the logic
shows the interpretation of the fields in
PCI Signal
inta#
intb#
intd#
inta#
intb#
intd#
inta#
intb#
intd#
intc#
intc#
intc#
PCI block transfer, the PCI inter-
SDRAM block transfer, the PCI
PCI block transfer, the PCI
0
1
0
1
Reads state of intx# pin:
0
1
Deassert intx#
Assert intx# (if enabled);
i.e., pull intx# pin to a low
logic level
Disable open-collector
output to intx#
Enable open-collector
output to intx#
No interrupt asserted
(intx# is high)
Interrupt is asserted
(intx# is low)
Programming
Figure 11-9. Conceptual realization of intx# pin con-
trol logic.
11.8
TM1300’s PCI interface can generate and respond to
several types of PCI bus commands.
the 12 possible commands and whether or not TM1300
can generate them.
Table 11-20. TM1300 PCI Commands as Initiator
Table 11-21
er or not TM1300 can respond to them.
Table 11-21. TM1300 PCI commands as target
The basic transfer mechanism on the PCI bus is a burst,
which consists of an address phase followed by one or
more data phases. In TM1300, the DSPCPU and ICP are
the only two units that can cause TM1300 to become a
PCI-bus initiator, i.e., only the DSPCPU and ICP can ac-
cess external resources.
11.8.1
When the DSPCPU reads or writes PC memory, the PCI
transaction has only a single data phase. A typical sin-
gle-data-phase
Figure
PRODUCT SPECIFICATION
Configuration read
Configuration write
Memory read
Memory read multiple
Memory write
Memory write and invalidate
I/O read
I/O write
Configuration read
Configuration write
Memory read
Memory write
Memory write and invalidate
Memory read line
Memory read multiple
INTx
IEx
ISx
TM1300 Responds To
TM1300 Generates
11-10. During the first clock period, the TM1300
PCI BUS PROTOCOL OVERVIEW
Single-Data-Phase Operations
lists the 12 possible commands and wheth-
read
operation
oc
I/O read
I/O write
Interrupt acknowledge
Special cycle
Dual address
Interrupt acknowledge
Special cycle
Dual address
Memory read line
TM1300 Ignores
TM1300 Cannot
is
Table 11-20
Generate
PCI Interface
illustrated
PCI intx#
11-15
lists
in