tm1300 NXP Semiconductors, tm1300 Datasheet - Page 325

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Floating-point add
SYNTAX
FUNCTION
DESCRIPTION
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the sum, and the IFZ flag in the PCSW is set. If
the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
operation. The update of the PCSW exception flags occurs at the same time as r dest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, r dest and the exception flags in PCSW are written;
otherwise, r dest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x80800000 (–1.175494351e-38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
The
The
The
[ IF r guard ] fadd r src1 r src2
if r guard then
faddflags
fadd
fadd
r dest
operation computes the sum r src1 +r src2 and stores the result into r dest . All values are in IEEE single-
Initial Values
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
(float)r src1 + (float)r src2
operation computes the exception flags that would result from an individual
fadd r60 r30
fadd r40 r60
IF r10 fadd r40 r80
IF r20 fadd r40 r80
fadd r40 r81
fadd r82 r83
fadd r84 r85
fadd r70 r70
fadd r80 r80
r dest
Operation
r90
r95
r111
r112
r113
r120
r125
PRODUCT SPECIFICATION
r100
r110
DSPCPU Operations for TM1300
r90
r95
no change, since guard is false
r110
r111
r112
INX flags set
r113
r120
r125
INX flags set
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
faddflags iadd dspiadd
dspidualadd readpcsw
0xc0000000 (–2.0)
0x00000000 (0.0)
0x40400000 (3.0), INX flag set
0x40400000 (3.0), IFZ flag set
0x00000000 (0.0), OFZ, UNF,
0xffffffff (QNaN), INV flag set
0x7f800000 (+INF), OVF,
0x01000000 (2.350988702e–38)
ATTRIBUTES
writepcsw
SEE ALSO
Result
fadd
fadd
.
writepcsw
causes an
fadd
falu
1, 4
No
22
—
2
3
A-39