tm1300 NXP Semiconductors, tm1300 Datasheet - Page 162

no-image

tm1300

Manufacturer Part Number
tm1300
Description
Tm-1300 Media Processor
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
tm1300-1.2
Quantity:
380
TM1300 Data Book
• The initiator asserted perr# or detected it asserted by
Table 11-3. Status register fields
DEVSEL (Device select timing). This read-only field
defines the slowest timing that will be used for the
devsel# signal when TM1300 is a target on the PCI bus.
Table 11-4
ings. These bits are hardwired to ‘01’ to indicate that
Table 11-4. DEVSEL encodings
TM1300 uses a ‘medium’ devsel# timing.
STA (Signaled target abort). TM1300’s PCI interface
sets this bit when it is a target device and aborts a trans-
action.
RTA (Receive target abort). TM1300’s PCI interface
sets this bit when it is the initiating device and the trans-
action is aborted by the target device. (All initiating devic-
es must implement this bit.)
RMA (Receive master abort). TM1300’s PCI interface
sets this bit when it is the initiating device and aborts a
transaction (except when the transaction is a special cy-
cle). (All initiating devices must implement this bit.)
SSE (Signaled system error). TM1300’s PCI interface
sets this bit when it asserts the serr# signal. (TM1300
can generate serr#, so this bit is implemented; devices
incapable of generating serr# need not implement SSE.)
Figure 11-5. Class-code register format.
11-6
Reserved Writes ignored; reads return 0
66M
UDF
FBC
DPD
DEVSEL
STA
RTA
RMA
SSE
DPE
Field
the target (during a write cycle).
DEVSEL
00
01
10
11
PCI bus speed (hardwired to 0
User-definable features (hardwired to 0
Fast back-to-back capable (hardwired to 0
unsupported)
Data parity detected
devsel# signal timing (hardwired to 1
Signaled target abort
Receive target abort
Receive master abort
Signaled system error
Detected parity error
shows the allowable encodings and mean-
Class Code
23
Characteristics
PRODUCT SPECIFICATION
Base Class Code
Reserved
Meaning
Medium
Slow
Fast
33-MHz)
‘medium’)
none)
15
Subclass Code
DPE (Detected parity error). TM1300’s PCI interface
sets this bit when it detects a parity error, even if parity
error handling is disabled. (The PAR bit in the command
register enables the handling of parity errors.)
11.6.5
The value in the Revision ID register is a read only value
chosen by the manufacturer to indicate product revi-
sions. For the TM1300 product family, the two MSBs of
the revision ID indicate the fab where the part was man-
ufactured. The next two bits indicate an all-layer revision
number, and the 4 LSBs indicate metal layer revisions.
Each all-layer revision adds 0x10 to the revision ID and
resets the 4 LSBs to ‘0’. Non-pin or -function compatible
TriMedia devices will use the same Revision ID conven-
tion, but with a revised Device ID.
Table 11-5. Actual revision ID values
11.6.6
The value in the Class Code register is read-only. Sys-
tem software uses the Class Code register to identify the
generic function of the device, and in some cases, the
Class Code can specify a register-level programming in-
terface.
Class Code consists of three 1-byte fields as shown in
Figure
Code, broadly classifies the function of the device. The
value of the middle byte, Subclass Code, identifies the
function more specifically. The value of the lower byte
specifies a register-level programming interface so that
device-independent software can interact with the de-
vice. The meanings of the Base Class byte values are
shown in
The value of Base Class is hardwired to 0x04 since
TM1300 is a multimedia device. Currently, there are no
specific register-level programming interfaces defined
for multimedia devices.
Table 11-7
vices. TM1300 is both a video and audio multimedia de-
vice, so its subclass value is hardwired to 0x80.
11.6.7
This field only matters when the MWI bit in configuration
space is set. The value of the Cache Line Size register
specifies the host system cache line size in units of 32-
Value (hex)
0x80
0x81
0x82
11-5. The value of the upper byte, Base Class
Table
Revision ID Register
Class Code Register
Cache Line Size Register
lists the defined subclasses of multimedia de-
TM1300 original mask - tm1f 1.0
TM1300 1st metal revision - tm1f 1.1
TM1300 2nd metal revision - tm1f 1.2
11-6.
7
Programming Interface
Product description
Philips Semiconductors
0

Related parts for tm1300