tm1300 NXP Semiconductors, tm1300 Datasheet - Page 26

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
1.4
In the table below, a pin name ending in a ‘#’ designates an active-low signal (the active state of the signal is a low
voltage level). All other signals have active-high polarity.
1-2
TRI_CLKIN
VDDQ
VSSQ
TRI_RESET#
BOOT_CLK
TESTMODE
SCANCPU
RESERVED1
RESERVED2
VREF_PCI
VREF_PERIPH
TRI_USERIRQ
TRI_TIMER_CLK
MM_CLK0
MM_CLK1
MM_A00
MM_A01
MM_A02
MM_A03
MM_A04
MM_A05
MM_A06
MM_A07
MM_A08
MM_A09
MM_A10
MM_A11
MM_A12
MM_A13
Pin Name
SIGNAL PIN LIST
BGA
W10
W12
W11
W13
Ball
G19
D20
E19
D19
C18
G20
H19
Y12
Y11
V12
Y13
Y14
L20
K20
L19
T20
P19
Y10
W9
W8
Y9
V9
Y8
Y7
F2
NORM3
NORM3
NORM3
NORM3
NORM3
NORM3
WEAK5
WEAK5
WEAK5
STRG5
STRG3
Type
Pad
N/A
N/A
N/A
N/A
PRODUCT SPECIFICATION
Mode
PWR
PWR
PWR
GND
OUT
OUT
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
Main input clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to
2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x,
5/4, 4/3, 3/2 or 2x the SDRAM clock frequency. Maximum recommended ppm level is
+/- 100 ppm or lower to improve jitter on generated clocks. Duty cycle should not
exceed 30/70% asymmetry.
Quiet VDD for the PLL subsystem. This pin should be supplied from VDD through a
low-Q series inductor. It should be bypassed for AC to VSSQ, using a dual capacitor
bypass (hi and low frequency AC bypass).
Quiet VSS for the PLL subsystem. Should be AC bypassed to VDDQ, but should
otherwise be left DC floating. It is connected on-chip to VSS. No external coil or
other connection to board ground is needed, such connection would create a
ground loop.
TM1300 RESET input. This pin can be tied to the PCI RST# signal in PCI bus sys-
tems. Upon receiving RESET, TM1300 initiates its boot protocol.
Used for testing purposes. Must be connected to TRI_CLKIN for normal operation.
Used for testing purposes. Must be connected to VSS for normal operation.
Used for testing purposes. Must be connected to VSS for normal operation.
Reserved pin. Has to be left unconnected for normal operation.
Reserved pin. Has to be left unconnected for normal operation.
VREF_PCI determines the mode of operation of the PCI pins listed in
VREF_PCI must be connected to 5V for use in a 5-V PCI signaling environment or to
VSS (0 V) for use in 3.3-V PCI signaling environment. The supply to this pin should be
AC bypassed and provide 40 mA of DC sink or source capability. Note that this pin
can not be directly connected to the PCI ‘I/O designated power pins’ in a dual
voltage PCI plug-in card. Board level conversion circuitry is required.
VREF_PERIPH determines the mode of operation of the I/O pins listed in
VREF_PERIPH should be connected to 5V if any of the listed I/O pins provided should
be 5-V input voltage capable. VREF_PERIPH should be connected to VSS (0-V) if all
listed I/O pins are 3.3-V only inputs. The supply to this pin should be AC bypassed and
provide 40 mA of DC sink or source capability.
General purpose level/edge interrupt input. Vectored interrupt source number 4.
External general purpose clock source for timers. Max. 40 MHz.
SDRAM output clock at 2x or 3x TRI_CLKIN frequency. Two identical outputs are pro-
vided to reliably drive several small memory configurations without external glue.
A series terminating resistor close to TM1000 is recommended to reduce ringing.
For driving a 50-ohm trace, a resistor of 27 to 33 ohm is recommended. We recom-
mend against using higher impedance traces in the SDRAM signals.
Main memory address bus; used for row and column addresses
(was ‘RESERVED2’ in TM1000 - also sometimes name MM_BA1)
(new in TM1300 - also named MM_64M_11 in some documents)
Miscellaneous System Interface
Main Memory Interface
Main Clock Interface
Description
Philips Semiconductors
Section
Section
1.6.
1.6.