tm1300 NXP Semiconductors, tm1300 Datasheet - Page 140

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
9.3
Seven TM1300 pins are associated with the AO unit. The
AO_OSCLK output is an accurately programmable clock
output intended to be used as the master system clock
for the external D/A subsystem. The other pins
(AO_SCK, AO_WS and AO_SDx) constitute a flexible
serial output interface. Using the AO MMIO registers,
these pins can be configured to operate in a variety of se-
rial interface framing modes, including but not limited to:
• Standard stereo I
• LSB first, with 1–16-bit data per channel.
• Complex serial frames of up to 512 bits/frame.
9.4
The AO unit consists of three major subsystems, a pro-
grammable sample clock generator, a DMA engine and
a data serializer.
The DMA engine reads 16 or 32-bit samples from mem-
ory using a double buffered DMA approach. The
DSPCPU initially assigns two full sample buffers contain-
ing an integral number of samples for all active channels.
The DMA engine retrieves samples from the first buffer
until exhausted and continues from the second buffer,
while requesting a new first sample buffer from the
DSPCPU, etc.
The samples are given to the data serializer, which
sends them out in a MSB first or LSB first serial frame for-
mat that can also contain 1 or 2 codec control words of
up to 16 bits. The frame structure is highly programmable
by a series of MMIO fields.
9.5
Figure 9-1
AO unit. At the heart of the clock system is a square
wave DDS (Direct Digital Synthesizer). The DDS can be
9-2
Figure 9-1. AO clock system and I/O interface
AO_WS, left & right data in a frame).
AO_OSCLK
AO_SCK
EXTERNAL INTERFACE
SUMMARY OF OPERATION
INTERNAL CLOCK SOURCE
AO_SDx
AO_WS
illustrates the different clock capabilities of the
(e.g. 256 f
(e.g. 64 f
s
s
)
)
2
S (MSB first, 1-bit delay from
PRODUCT SPECIFICATION
Parallel to Serial Converter
div N+1
div N+1
SER_MASTER
8
7
16
16
32
WSDIV
SCKDIV
RIGHT[15:0]
LEFT[15:0]
AO_CC[31:0]
programmed to emit frequencies from approx. 1 Hz to 80
MHz with a sub Hertz resolution.
The output of the DDS is always sent to the AO_OSCLK
output pin. This output is intended to be used as the
256f
converters, such as the Philips SAA7322, or codecs
such as the AD1847, CS4218, or UAD1340.
The TM1300 DDS frequency is set by writing to the FRE-
QUENCY MMIO register. The programmer is free to
change the FREQUENCY setting dynamically, in order
to adjust the outgoing audio sample rate. In ATSC trans-
port stream decoding, this is the method by which the
system software locks audio output sample rate to the
original program provider sample rate.
Depending on bit 31 (MSB), the DDS runs in one of the
two following modes:
• bit 31 = 1 (standard mode)
• bit 31 = 0 (TM1000 compatibility mode)
9.5.1
This mode was first available in the TM1100. In this
mode, a high quality, low-jitter AO_OSCLK is generated.
The setting of the FREQUENCY register to accomplish a
given AO_OSCLK frequency is given by the formula:
This mode, and the above formula, should be used for all
new software development on TM1300.
Table 9-2. Clock system setting (f
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
9 DSPCPUCLK
FREQUENCY
s
f
s
or 384f
0
0
TM1300 Standard Mode
s
OSCLK
256fs
256fs
384fs
384fs
system clock source for oversampling D/A
31
=
SCK
64fs
64fs
64fs
64fs
2
31
Square Wave DDS
Philips Semiconductors
FREQUENCY
+
------------------------------- -
9 f
f
FREQUENCY
OSCLK
2187991971
2191574340
2208246133
2213619686
DSPCPU
DSPCPU
2
32
=133 MHz)
SCKDIV
3
3
5
5
0