tm1300 NXP Semiconductors, tm1300 Datasheet - Page 86

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Reading the LRU bits produces a 32-bit result with the
format shown at the bottom of
nificant ten bits contain the state of the LRU bits when the
ld32 was executed. See
tions,”
Note that the tag_i_mux and set fields in the address for-
mats of
struction cache in TM1300. These fields will allow future
implementations with larger instruction caches to use a
compatible mechanism for reading instruction cache in-
formation. The tag_i_mux field can accommodate a
cache of up to 16-way set-associativity, and the set field
can accommodate a cache with up to 512 sets. For
TM1300, the following constraints of the values of these
fields must be observed:
1. 0
2. 0
5.4.9
Like the data cache, the instruction cache allows up to
one-half of its blocks to be locked. A locked block is nev-
er chosen as a victim by the replacement algorithm; its
contents remain undisturbed until the locked status is
changed explicitly by software. Thus, on TM1300, up to
16 KB of the cache can be used as a high-speed instruc-
tion ‘ROM.’ Only four out of eight blocks in any set can
be locked.
The MMIO registers IC_LOCK_ADDR, IC_LOCK_SIZE,
and IC_LOCK_CTL—shown in
define and enable instruction locking in the same way
that the similarly named data-cache locking registers are
used.
tails of cache locking; they are not repeated here.
Figure 5-10. Required address format for reading instruction-cache tags and status.
Figure 5-11. Result formats for reads from the instruction-cache region of the MMIO aperture.
Figure 5-12. Formats of the registers that control instruction-cache locking.
5-10
I-Cache Status-Read Result Format
MMIO_BASE
0x10 0210
0x10 0214
0x10 0218
I-Cache Tag-Read Result Format
Section 5.3.7, “Cache Locking,”
offset:
tag_i_mux
set
for a description of the LRU bits.
Figure 5-10
To Read Tag & Valid Bit
Cache Locking
63
To Read LRU Bits
IC_LOCK_CTL (r/w)
IC_LOCK_ADDR (r/w)
IC_LOCK_SIZE (r/w)
7
are larger than necessary for the in-
Section 5.6.7, “LRU Bit Defini-
PRODUCT SPECIFICATION
Figure
Figure
31
31
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
5-11. The least-sig-
31
0 0 0 0 0 0
0 0 0 0 0 0
5-12—are used to
describes the de-
27
MMIO_BASE
MMIO_BASE
27
27
IC_LOCK_ADDRESS
23
0 0
0 0
23
23
0 0 0 0 0 0
0 0 0 0 0 0
19
0
Setting the IC_LOCK_ENABLE bit (in IC_LOCK_CTL) to
‘1’ causes the following sequence of events:
1. The instruction cache invalidates all blocks in the
2. The instruction cache fetches all blocks in the lock
3. Cache locking is activated so that the locked blocks
The only difference between this sequence and the ini-
tialization sequence for data-cache locking is that dirty
blocks (which cannot exist in the instruction cache) are
not written back first.
Programmer’s note: Programmers (or compilers) must
combine all instructions that need to be locked into the
single linear instruction-locking address range.
The special iclr operation also removes locked blocks
from the cache. If blocks are locked in the instruction
cache, then instruction cache locking should be disabled
in software (by writing ‘0’ to IC_LOCK_CTL) before an
iclr operation is issued.
Locking should not be enabled by PCI accesses to the
MMIO register.
5.4.10
When TM1300 is reset, the instruction cache executes
an initialization and processor boot sequence. While re-
set is asserted, the instruction cache forces NOP opera-
tion to the DSPCPU, and the program counter is set to
the default value reset_vector. When reset is deassert-
ed, the initialization and boot sequence is as follows.
0 0 0
cache.
range (defined by IC_LOCK_ADDR and
IC_LOCK_SIZE) from main memory into the cache.
cannot be victims of the replacement algorithm.
19
VALID
19
15
0 0 0 0 0 0 0 0
0
1 0 0 0 0
Instruction Cache Initialization and
Boot Sequence
0 0 0 0 0 0
0 0
TAG_I_MUX
15
15
0 0
0
11
0 0
11
IC_LOCK_SIZE
11
0 0 0 0 0 0
0 0 0 0 0 0
TAG
Philips Semiconductors
7
SET
SET
7
IC_LOCK_ENABLE
7
LRU
3
0
0 0 0 0 0 0
0 0 0 0 0 0
3
0 0
0 0
reserved
3
0
0
0