tm1300 NXP Semiconductors, tm1300 Datasheet - Page 175

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

SDRAM Memory System
12.1
• Support of 64-Mbit SDRAMs organized in x16 and
• Partial support of 64-Mbit SDRAMs organized in x8
• External MM_MATCHOUT to MM_MATCHIN line is
12.2
TM1300 connects to its local memory system with a ded-
icated memory bus, shown in
faces only with SDRAM or SGRAM (synchronous graph-
ics DRAM) with its DSF pin tied low; TM1300 is the only
master on this bus.
A variety of device types, speeds, and rank
supported allowing a wide range of TM1300 systems to
be built.
tures.
The main memory interface provides all control and data
signals with sufficient drive capacity for a glueless con-
nection to a 143-MHz memory system with up to four
memory devices. Note that memory-system speed can
be different from TM1300 core speed; the ratio between
the memory system clock and TM1300 core clock is pro-
grammable.
With current memory technology, TM1300 supports a
glueless memory interface of up to 32 MBytes with four
4 1M 16 SDRAM chips (four devices with 4 banks of
one million words, each 16 bits wide) or four 4x512Kx32
or two 8 1M 16 SDRAM devices. Larger memories re-
quire a lower memory system clock frequency (though
the TM1300 core clock can be higher).
1.
128-Mbit organized in x32.
and 128-Mbit SDRAMs organized in x16.
no longer required.
In this document, the term ‘rank’ is used to refer to a
group of memory devices that are accessed together.
Historically, the term ‘bank’ has been used in this con-
text; to avoid confusion, this document uses bank to re-
fer to on-chip organization (SDRAM devices have two
or four internal banks) and rank to refer to off-chip, sys-
tem-level organization.
NEW IN TM1300
TM1300 MAIN MEMORY OVERVIEW
Table 12-1
summarizes the memory system fea-
Figure
12-1. This bus inter-
by Eino Jacobs, Chris Nelson, Thorwald Rabeler, Luis Lucas
1
sizes are
Table 12-1. Memory System Features
12.3
TM1300’s local main memory is just one of three aper-
tures into the 4-GB address space of the DSPCPU:
• SDRAM (0.5 to 64 MB in size),
• MMIO (2 MB in size), and
• PCI (any address not in SDRAM or MMIO).
MMIO registers control the positions of the address-
space apertures. The SDRAM aperture begins at the ab-
solute
DRAM_BASE and extends upward to the address spec-
ified in the DRAM_LIMIT register. If the SDRAM aperture
overlaps the memory hole, the memory hole is ignored.
The MMIO aperture begins at the address in
MMIO_BASE, which defaults to 0xEFE00000 after pow-
er-up, and extends upwards 2 MB. (See
“DSPCPU Architecture,”
addresses that fall outside these two apertures are as-
sumed to be part of the PCI address aperture.
PRODUCT SPECIFICATION
Data width
Number of ranks
Memory size
Devices
supported
Clock rate
Bandwidth
Glueless interface • Up to 4 chips at 143 MHz (e.g., 32 MB
Signal levels
Characteristic
MAIN-MEMORY ADDRESS
APERTURE
address
32 bits
Four chip-select signals support up to
four ranks
From 512 KB to 64 MB
• Jedec SGRAM (DSF tied low)
• Jedec SDRAM ( 4, 8, 16, 32)
• PC100/133
Up to 143 MHz SDRAM speed (program-
mable ratio between TM1300 core clock
and memory system clock)
572 MB/sec (at 143 MHz)
• Up to 8 chips at 133 MHz (e.g., 64 MB
3.3-V LVTTL
specified
memory with 4x512Kx32 SDRAM)
memory with 4x1Mx16 SDRAM)
for a detailed discussion.) All
Chapter 12
in
Comments
the
MMIO
Chapter 3,
register
12-1