tm1300 NXP Semiconductors, tm1300 Datasheet - Page 307

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Invalidate data cache block
SYNTAX
FUNCTION
DESCRIPTION
bit, the block is not written back to main memory. The target block of
contains the byte addressed by r src1 + d . The d value is an opcode modifier, must be in the range –256 to 252
inclusive, and must be a multiple of 4.
dinvalid
bits of locked blocks.
and by causing all non-empty copyback buffers to be emptied to main memory.
operation is carried out or not. If the LSB of r guard is 1, the operation is carried out; otherwise, it is not carried out.
EXAMPLES
r10 = 0
r20 = 1
The
Stall cycles are taken as necessary to complete the invalidate operation. If the target block is not in the cache,
dinvalid
dinvalid
The
[ IF r guard ] dinvalid( d ) r src1
if r guard then {
}
addr
if dcache_valid_addr(addr) then {
}
dinvalid
dinvalid
dcache_reset_valid_addr(addr)
dcache_reset_dirty_addr(addr)
r src1 + d
has no effect and no stall cycles are taken.
has no effect on blocks that are in the non-cacheable SDRAM aperture.
ensures coherency between caches and main memory by discarding all pending prefetch operations
Initial Values
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls if the
operation resets the valid and dirty bit of a block in the data cache. Regardless of the block’s dirty
dinvalid
does not change the replacement status of data-cache blocks.
dinvalid(0) r30
IF r10 dinvalid(4) r40
IF r20 dinvalid(8) r50
Operation
PRODUCT SPECIFICATION
dinvalid
DSPCPU Operations for TM1300
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
no change and no stall cycles, since
guard is false
is the block in the data cache that
dinvalid
ATTRIBUTES
SEE ALSO
Result
dcb
does clear the valid
dinvalid
–256..252 by 4
dmemspec
7 bits
206
1
3
5
A-21