tm1300 NXP Semiconductors, tm1300 Datasheet - Page 144

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Figure 9-4
CS4218 codec. It is obtained by setting POLARITY=1,
LEFTPOS=0, RIGHTPOS=32, DATAMODE=0, SS-
POS=0, CLOCK_EDGE=1, WS_PULSE=1, CC1_POS =
16, CC1_EN=1, CC2_POS=48, CC2_EN=1.
Note that frames are generated (externally or internally)
even when TRANS_ENABLE is de-asserted. Writes to
CC1
TRANS_ENABLE is asserted. The ‘first’ CC values will
then go out on the next frame. For a summary of codec
control fields see
9.9
The AO unit autonomously reads samples from memory
in 16 or 32 bit-per-sample memory formats, as shown in
Figure 9-5
are retrieved and used as described in
Table 9-9. Operating modes and memory formats
9-6
Figure 9-4. Example codec frame layout for a Crystal Semi, CS4218.
AO_SCK
NR_CHAN MODE
00
00
01
01
10
10
11
11
AO_WS
16-bit, stereo,
NR_CHAN=00
16-bit, stereo,
NR_CHAN=10
32-bit, stereo,
NR_CHAN=00
Figure 9-5. AO memory DMA formats.
AO_SDx
and
MEMORY DATA FORMATS
shows a 64-bit frame suitable for use with the
for some example modes. Memory samples
0
stereo
stereo
stereo
stereo
mono
mono
mono
mono
left channel data
1
CC2
SD1.left
SD1.left
2
Table 9-8
adr
adr
3
SD1.left, SD1.right, SD2.left, SD2.right,
SD1.left, SD1.right, SD2.left, SD2.right,
SD3.left, SD3.right, SD4.left, SD4.right.
SD1.left, SD1.right, SD2.left, SD2.right
destination of successive samples
should
SD1.left, SD2.left, SD3.left, SD4.left
n
n
SD1.left
adr
n
SD1.left, SD2.left, SD3.left
(16)
PRODUCT SPECIFICATION
SD1.right
SD1.right
n
SD1.left, SD1.right
SD3.left, SD3.right
SD1.left, SD2.left
adr+2
adr+2
lsb
only
15
16
SD1.left
n
n
be
CC1(16)
Table
SD1.left
SD2.left
adr+4
adr+4
done
9-9. Suc-
n+1
SD1.right
n
adr+4
after
SD1.right
lsb
SD2.right
31
n
adr+6
adr+6
32
right channel data
n+1
n
cessive samples are always read from increasing mem-
ory
LITTLE_ENDIAN bit in the AO_CTL register determines
the byte order of retrieved 16 or 32-bit samples. Refer to
Appendix C, “Endian-ness,”
ventions.
AO hardware implements a double buffering scheme to
ensure that there are always samples available to trans-
mit, even if the DSPCPU is highly loaded and slow to re-
spond to interrupts. The DSPCPU software assigns 2
equal size buffers by writing a base address and size to
the MMIO control fields described in
Section 9.10, “Audio Out Operation,”
ware/software synchronization.
If SIGN_CONVERT is set to one, the MSB of the memo-
ry data is inverted, which is equivalent to translating from
offset binary representation to two’s complement. This
allows the use of an external two’s complement 16-bit D/
A converter to generate audio from 16-bit unsigned sam-
ples. This MSB inversion also applies to the ‘0’ values
transmitted to non-active output channels.
Note that the AO hardware does not support A-law or -
law eight-bit data formats. If such formats are desired,
the DSPCPU should be used to convert from A-law or -
law data to 16-bit linear data.
SD1.left
address
SD3.left
adr+8
adr+8
n
n+2
SD1.left
(16)
n
adr+8
47
lsb
SD1.right
locations.
SD3.right
n+1
48
adr+10
adr+10
for details on byte ordering con-
n+2
n
CC2(16)
Philips Semiconductors
The
SD1.left
SD1.left
adr+12
adr+12
Figure
62
n+3
n+1
SD1.right
for details on hard-
setting
lsb
adr+12
63
0
SD1.right
SD1.right
left data
9-6. Refer to
n+1
1
adr+14
adr+14
of
n+1
n+3
n+1
(16)
the