zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 10

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
HOLDOVER
C34/C44
SECOR
Name
LOCK
GND
VDD
C20i
VDD
NC
NC
NC
OE
DS
CS
IC
Positive Power Supply
No internal bonding Connection. Leave unconnected.
Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master
Clock Oscillator. The clock oscillator should be connected directly (not AC
coupled) to the C20i input and it must supply clock with duty cycle that is not
worse than 40/60%.
Ground
Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is
programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz
(for DS3 applications) when E3DS3/OC3 is high, or to be either 8.592 MHz or
11.184 MHz when E3DS3/OC3 is low. See description of E3DS3/OC3 and
E3/DS3 inputs for details. In Software Control the functionality of this output is
controlled by Control Register 2 (Table 8 "Control Register 2 (R/W)").
Positive Power Supply
Holdover Indicator (CMOS output). Logic high at this output indicates that the
device is in Holdover mode.
No internal bonding Connection. Leave unconnected.
Lock Indicator (CMOS output). Logic high at this output indicates that
ZL30407 is locked to the input reference. See LOCK bit description in Status
Register 1 and Section 3.2.4, Lock Indicator (LOCK) for details.
No internal bonding Connection. Leave unconnected.
Data Strobe (5 V tolerant input). This input is the active low data strobe of the
processor interface.
Internal Connection. Connect to ground.
Secondary Reference Out of Range (Output). Logic high at this pin indicates
that the Secondary Reference is off the PLL centre frequency by more than
r12 ppm. These thresholds support Stratum 3 applications. See SECOR bit
description in Status Register 1 for details.
Output Enable (Input). Logic high on this input enables C19, F16, C16, C8,
C6, C4, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output
clocks pins into a high impedance state.
Chip Select (5 V tolerant input). This active low input enables the
microprocessor interface. When CS is set to high, the microprocessor interface
is idle and all Data Bus I/O pins will be in a high impedance state.
Zarlink Semiconductor Inc.
ZL30407
10
Description
Data Sheet