zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 31

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Address: 1A H
Address: 20 H
7-0
7-5
4-3
Bit
Bit
2
1
0
InpFreq1-0
FPOA7 - 0
Name
Name
PAFL
RSV
RSV
PAH
Fine Phase Offset Adjustment. This register allows phase offset
adjustment of all output clocks and frame pulses (C16o, C8o, C4o, C2o,
F16o, F8o, F0o, C155, C19o, C34/44, C1.5o, C6o) relative to the active input
reference. The adjustment can be positive (advance) or negative (delay) with
a nominal step size of 477 ps (61.035 ns / 128). Changes to the offset values
are filtered before they propagate to the PLL outputs. The rate of phase
change is determined by the bandwidth of the selected filter and is limited to
the level listed in the Table , “Performance Characteristics*” on page 49.
The phase offset value is a signed 2’s complement number e.g.:
Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH
Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H
Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays
all clocks
Reserved
Input Frequency. These two bits identify the Primary Reference Clock frequency.
Reserved
Primary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when the reference frequency is:
•
•
•
This status bit is intended to provide software compatibility with the ZL30402. It is not
required for new designs.
Table 17 - Primary Acquisition PLL Status Register (R)
-
-
-
-
lost completely
drifts more than r30 000 ppm off from the nominal frequency
a large phase hit occurs on the reference clock
00 = 19.44 MHz
01 = 8 kHz
10 = 1.544 MHz
11 = 2.048 MHz
Table 16 - Fine Phase Offset Register (R/W)
Zarlink Semiconductor Inc.
ZL30407
Functional Description
31
Functional Description
Data Sheet
Default
00000
000