zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 21

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

3.6
The ZL30407 can be controlled by a microprocessor or by an ASIC type of device that is connected directly to the
hardware control pins. If the HW pin is tied low (see Figure 7 "Hardware and Software Control Options"), an 8-bit
Motorola type microprocessor may be used to control PLL operation and check its status. Under software control,
the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits.
The output pins LOCK, HOLDOVER, PRIOR and SECOR are always active and they provide current status
information whether the device is in microprocessor or hardware control. Software (microprocessor) control
provides additional functionality that is not available in hardware control such as:
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3.7
The ZL30407 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990,
which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made
up of four basic elements, Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers
(TDR) and all these elements are implemented on the ZL30407.
Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the
information required for a JTAG test system to access the ZL30407's boundary scan circuitry. The file is available
for download from the Zarlink Semiconductor web site: www.zarlink.com.
4.0
The ZL30407 offers Hardware and Software Control options that simplify the design of basic or complex clock
synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing
cards without extensive programming. The complete set of control and status functions for each mode are shown in
Figure 7 "Hardware and Software Control Options".
6 Hz and 12 Hz PLL loop filter selection
output clock phase adjustment
master clock frequency calibration
extended access to status registers.These registers are also accessible when the ZL30407 operates under
Hardware control.
Microprocessor Interface
JTAG Interface
Hardware and Software Control
Zarlink Semiconductor Inc.
ZL30407
21
Data Sheet