zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 32

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Address: 28 H
Address: 40 H
Address: 41 H
Address: 42 H
7-5
4-3
Bit
2
1
0
7-0
7-0
Bit
Bit
7-0
Bit
InpFreq1-0
MCFC23 - 16
Name
SAFL
MCFC31 - 24
RSV
RSV
SAH
MCFC15 - 8
Name
Name
Name
Table 19 - Master Clock Frequency Calibration Register 4 (R/W)
Table 20 - Master Clock Frequency Calibration Register 3 (R/W)
Table 21 - Master Clock Frequency Calibration Register 2 (R/W)
Table 18 - Secondary Acquisition PLL Status Register (R)
Reserved
Input Frequency. These two bits identify the Secondary Reference Clock frequency.
Reserved
Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition
PLL enters Holdover mode. Holdover mode is entered when reference frequency is:
•
•
•
This status bit is intended to provide software compatibility with the ZL30402. It is not
required for new designs.
-
-
-
-
lost completely
drifts more than r30 000 ppm off the nominal frequency
a large phase hit occurs on the reference clock
Master Clock Frequency Calibration. This most significant byte
contains the 31st to 24th bit of the Master Clock Frequency
Calibration Register. See Applications section 4.2 for a detailed
description of how to calculate the MCFC value.
Master Clock Frequency Calibration. This byte contains the 23rd
to 16th bit of the Master Clock Frequency Calibration Register.
Master Clock Frequency Calibration. This byte contains the 15th
to 8th bit of the Master Clock Frequency Calibration Register.
00 = 19.44 MHz
01 = 8 kHz
10 = 1.544 MHz
11 = 2.048 MHz
Zarlink Semiconductor Inc.
ZL30407
Functional Description
Functional Description
Functional Description
32
Functional Description
Data Sheet
Default
Default
Default
00000
00000
00000
000
000
000