zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 35

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

5.1.2
The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses
its single reference clock unexpectedly. The sequence starts with the reference clock transitioning from OK --> FAIL
at a time when ZL30407 operates in Normal mode (as is shown in Figure 10). This failure is detected by the active
Acquisition PLL based on the following FAIL criteria:
•
•
After detecting any of these anomalies on a reference clock the Acquisition PLL will switch itself into Holdover mode
forcing the Core PLL to automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0
and HOLDOVER = 1.
There are two possible returns to Normal mode after the reference signal is restored:
•
•
The transition from Auto Holdover to Normal mode is performed as “hit-less” recovery for 1.544 MHz, 2.048 MHz
and 19.44 MHz references. For the 8 kHz input reference, the recovery from Auto Holdover state must transition
through the Holdover state to preserve “hit-less” recovery (for details see Section 5.1.3 on page 36).
Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm
(±3%).
Single phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock
With the AHRD (Automatic Holdover Return Disable) bit set to 0. In this case the Core PLL will automatically
return to the Normal state after the reference signal recovers from failure. This transition is shown on the
state diagram as a FAIL --> OK change. This change becomes effective when the reference is restored and
there have been no phase hits detected for at least 64 clock cycles for the 1.544/2.048 MHz reference, 512
clock cycles for the 19.44 MHz reference and 1 clock cycle for the 8 kHz reference.
With the AHRD bit set to 1 to disable automatic return to Normal and the change of MHR (Manual Holdover
Release) bit from 0 to 1 to trigger the transition from Auto Holdover to Normal. This option is provided to
protect the Core PLL and its stored holdover value against toggling between Normal and Auto Holdover
states in case of an intermittent quality reference clock. In the case when MHR has been changed when the
reference is still not available (Acquisition PLL in Holdover mode) the transition to Normal state will not occur
and MHR 0 to 1 transition must be repeated.
RESET = 1
Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL
RESET
Figure 10 - Automatic Entry into Auto Holdover State and Recovery into Normal Mode
unconditional return from
MS2,MS1 = 10 forces
any state to Free-run
FREE-
RUN
10
MS2,MS1 = 00
MS2,MS1 = 01
OR
MS2,MS1 = 01 OR
RefSel change
HOLD-
OVER
01
Zarlink Semiconductor Inc.
MS2,MS1 = 00
Ref: OK AND
ZL30407
{AUTO}
35
RefSel Change
MS2,MS1 = 01
NORMAL
00
OR
Ref: OK-->FAIL AND
MS2,MS1 = 00
{AUTO}
HOLD-
AUTO
OVER
Ref: FAIL-->OK AND
MS2,MS1 = 00 AND
AHRD = 0
{AUTO}
Ref: FAIL-->OK AND
MS2,MS1 = 00 AND
AHRD = 1 AND MHR = 1
{MANUAL}
AHRD = 1 AND
MHR = 0
OR
Data Sheet