zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 14

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

3.2.3
Phase slope limiting is achieved by clamping the size of the error term from the phase detector. Limiting the size of
the error term means that the output clocks move slowly in phase as the PLL aligns to phase transients on the input
reference or transients caused by reference rearrangement. This increases the time required to achieve phase
lock, but it is necessary to allow for downstream adjustments and so is called for in network standards such as
G.813, GR-1244 and GR-253. Because the ZL30407 nulls out the phase offset between the output clocks and the
selected reference upon reference rearrangement or return from holdover, the phase slope limiting feature will
generally not come into play. If the pin RefAlign is pulled low to align the equivalent ZL30407 output clock to the
selected reference, a large phase error will have to be corrected. In this case phase slope limiting will be active,
limiting the output phase slope to 0.727 ppm for the 0.1 Hz filter mode, 31 ppm for the 1.5 Hz and the 6 Hz filter
mode. In the 12 Hz mode there is no phase slope limiting. Consequently an output phase slope greater than 31
ppm may occur, for example, in locking to an orthogonal 8 kHz reference.
3.2.4
The ZL30407 is considered locked (LOCK = 1) when the residual phase movement after declaring locked condition
does not exceed standard wander generation MTIE and TDEV tests. The ZL30407’s phase locking mechanism
allows it to lock within the specified locking times to references with a fractional frequency offset of up to r20 ppm.
Locking time for different filters and pulling ranges is listed in “Performance Characteristics*” on page 49.
3.2.5
When the ZL30407 finishes locking to a reference an arbitrary phase difference will remain between its output
clocks and its reference; this phase difference is part of the normal operation of the ZL30407. If so desired, the
output clocks can be brought into phase alignment with the PLL reference (see Figure 21 on page 47) by using the
RefAlign control bit/pin.
3.2.5.1
If the ZL30407 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought
into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the
procedures below:
1. For 0.1 Hz filtering applications (FCS = 1, FCS2 = 0)
After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks
to remove the static phase error. The PLL will then begin the normal locking procedure. The LOCK pin will go low 5
sec after the reference realignment is initiated and will remain low for 10 sec.
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Wait until the ZL30407 LOCK indicator is high, indicating that it is locked
Pull FCS low
Pull Ref/Align low
Hold RefAlign low for 250 Ps
Pull RefAlign high
Wait until the LOCK indicator goes high
Pull FCS high
Phase Slope Limiters
Lock Indicator (LOCK)
Reference Alignment (RefAlign)
Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference
Zarlink Semiconductor Inc.
ZL30407
14
Data Sheet