zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 26

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Address: 01 H
Bit
7
6
5
4
3
2
1
0
HOLDOVER
SECOR
PRIOR
Name
LOCK
FLIM
RSV
RSV
RSV
Primary Reference Out of Range. This output goes high when:
•
•
Secondary Reference Out of Range. Functionally, this bit is equivalent to the
PRIOR bit for Primary Acquisition PLL.
Lock. This bit goes high when the Core PLL completes the phase locking process to
the input reference clock (see Section 3.2.4, Lock Indicator (LOCK) for details). After
achieving lock, this bit will go low if the ZL30407 enters Holdover mode, Automatic
Holdover mode or Free-run mode, or if the Core PLL phase detector accumulates
more than 22 Ps of phase error, or if the RefAlign control bit/pin is taken low.
Note that the indication of the LOCK status pin is a logical combination of the LOCK
status bit and the FLIM status bit. Please see the FLIM status bit description.
Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection of
reference failure and subsequent transition from Normal to Holdover mode takes
approximately: 0.75 Ps for 19.44 MHz reference, 0.85 Ps for 2.048 MHz reference,
1.5 Ps for 1.544 MHz reference and 130 Ps for 8 kHz reference.
Reserved
Frequency Limit. This bit goes high when the Core PLL is pulled by the input
reference signal to the edge of its frequency tracking range set at r104 ppm. This bit
may change state momentarily in the event of large jitter or wander excursions
occurring when the input reference is close to the frequency limit range.
When the FLIM bit goes high it will cause the LOCK status pin to go low, but it will not
cause the LOCK status bit to go low.
Reserved
Reserved
the primary reference is off its nominal frequency by more than r12 ppm. The
frequency offset monitor updates internally every 10 sec and will change state
after two matching measurements (PASS/PASS or FAIL/FAIL). This is in full
compliance with the GR-1244-CORE requirement of 10 to 30 sec Reference
Validation Time. This output returns to zero when the reference frequency is
requalified within r9.2 ppm of the nominal frequency (monitor circuit has built-in
hysteresis). In an extreme case, when over time the Master Clock oscillator
drifts r4.6 ppm the switching thresholds will change as well, as is shown in
Figure 8.
the reference impairment detector detects large frequency offset (greater than
3%) or large change in a single cycle period (greater than 30%). In both cases
detector will disqualify the reference and reset the 10 sec internal timer.
Table 7 - Status Register 1 (R)
Zarlink Semiconductor Inc.
ZL30407
26
Functional Description
Data Sheet