zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 24

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

In addition to the Control bits shown in Figure 7 "Hardware and Software Control Options", the ZL30407 has a
number of bits and registers that are accessed infrequently e.g., 6 Hz and 12 Hz PLL loop filter selection, Phase
Offset Adjustment or Master Clock Frequency Calibration. These additional control options add flexibility to the
ZL30407.
The ZL30407 has a number of status bits that provide more comprehensive monitoring of the internal operation
than is available in Hardware control (see Figure 7 "Hardware and Software Control Options"). The HOLDOVER,
PRIOR and SECOR bits perform the same function as their equivalent status pins. The function of the LOCK status
bit is not identical to the function of the LOCK status pin, see the description of the LOCK status bit and the FLIM
status bit for details. The FLIM bit indicates that the output frequency of the Core PLL has reached its upper or
lower limit. The PAH and SAH status bit show entry of the Primary and Secondary acquisition PLLs into Holdover
mode. See section 3.2.4 for detailed description of the status bits. Under software control, the status pins are
always enabled and they can be used to trigger hardware interrupts.
4.2.2
Addresses: 00H to 6FH
Note: The ZL30407 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read.
Address
hex
1A
00
01
04
06
07
0F
13
14
19
20
28
40
41
42
43
11
ZL30407 Register Map
Control Register 1
Status Register 1
Control Register 2
Phase Offset Register 2
Phase Offset Register 1
Device ID Register
Control Register 3
Clock Disable Register 1
Clock Disable Register 2
Core PLL Control Register
Fine Phase Offset Register
Primary Acquisition PLL
Status Register
Secondary Acquisition PLL
Status Register
Master Clock Frequency
Calibration Register - Byte 4
Master Clock Frequency
Calibration Register - Byte 3
Master Clock Frequency
Calibration Register - Byte 2
Master Clock Frequency
Calibration Register - Byte 1
Register
Table 5 - ZL30407 Register Map
Read
Write
Zarlink Semiconductor Inc.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
ZL30407
24
RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign
PRIOR, SECOR, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv
E3DS3/OC3, E3/DS3, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, OffEn, C16POA10, C16POA9, C16POA8
C16POA7, C16POA6, C16POA5, C16POA4, C16POA3,
C16POA2, C16POA1, C16POA0
0111 0000
rsv, rsv, C1.5POA2, C1.5POA1, C1.5POA0, 0, 0, FCS2
0, 0, C16dis, C8dis, C4dis, C2dis, C1.5dis,0
0, 0, 0, F8odis, F0odis, F16odis, C6dis, C19dis
0, 0, 0, 0, 0, MHR, AHRD, 0
FPOA7, FPOA6, FPOA5, FPOA4, FPOA3, FPOA2,
FPOA1, FPOA0
rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, PAH,PAFL
rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, SAH, SAFL
MCFC31, MCFC30, MCFC29, MCFC28, MCFC27,
MCFC26, MCFC25, MCFC24,
MCFC23, MCFC22, MCFC21, MCFC20, MCFC19,
MCFC18, MCFC17, MCFC16
MCFC15, MCFC14, MCFC13, MCFC12, MCFC11,
MCFC10, MCFC9, MCFC8
MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2,
MCFC1, MCFC0
Function
Data Sheet