zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 36

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

5.1.3
The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of the
8 kHz reference. The failure conditions triggering this transition are described in section 4.1.2. When in the Auto
Holdover state, the ZL30410 can return to Normal mode automatically but this transition may exceed Output Phase
Continuity limits specified in the table Performance Characteristics* on page 49. This probable time interval error is
avoidable by forcing the PLL into Holdover state immediately after detection of the 8 kHz reference failure. While in
Holdover state the ZL30410 will continue monitoring quality of the input reference (if a proper r4.6 ppm Master
Clock oscillator is employed) and after detecting the presence of a valid reference it can be switched into Normal
state. When the Master Clock Oscillator accuracy exceeds r4.6 ppm range (leading to inaccurate internal
out-of-range detection) then an external method for detecting the presence of the clock should be employed to
switch the ZL30410 into Normal state (0.1 sec after detecting the presence of a valid 8 kHz reference).
Figure 11 - Recovery Procedure From a Single 8 kHz Reference Failure by Transitioning Through
RESET = 1
NORMAL
Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER -->
RESET
unconditional return from
MS2,MS1 = 10 forces
any state to Free-run
FREE-
RUN
10
MS2,MS1 = 00
MS2,MS1 = 01
OR
MS2,MS1 = 01 OR
RefSel change
HOLD-
OVER
01
Zarlink Semiconductor Inc.
MS2,MS1 = 00
Ref: OK AND
the Holdover State
ZL30407
{AUTO}
36
When HOLDOVER 0-->1
then set MS2,MS1 = 01
NORMAL
00
Ref: OK-->FAIL AND
MS2,MS1 = 00
{AUTO}
HOLD-
AUTO
OVER
AHRD = 1 AND MHR = 0
automatic return to Normal mode
Set AHRD = 1 to disable
Data Sheet