zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 30

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Address: 14 H
Address: 19 H
7-5
7-3
Bit
Bit
4
3
2
1
0
2
1
0
F16odis
AHRD
Name
C19dis
F8odis
F0odis
MHR
RSV
RSV
Name
C6dis
RSV
Reserved
Manual Holdover Release. A change form 0 to 1 on the MHR bit will release
the Core PLL from Auto Holdover when automatic return from Holdover is
disabled (AHRD is set to 1). This bit is level sensitive and it must be cleared
immediately after it is set to 1 (next write operation). This bit has no effect if
AHRD is set to 0.
Automatic Holdover Return Disable. When set high, this bit inhibits the
Core PLL from automatically switching back to Normal mode from Auto
Holdover state when the active Acquisition PLL regains lock to its input
reference. The active Acquisition PLL is the Acquisition PLL to which the
Core PLL is currently connected.
For the 8 kHz input reference, the recovery from Auto Holdover state must
transition through the Holdover state to preserve “hit-less” recovery. To
guarantee this transitioning, the AHDR bit should be set high permanently to
prevent automatic return to Normal mode.
Reserved
Reserved
F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz
122 ns active high framing pulse output.
F0o Frame Pulse Disable. When set high, this bit tristates the 8 kHz
244 ns active low framing pulse output.
F16o Frame Pulse Disable. When set high, this bit tristates the 8 kHz
61 ns active low framing pulse output.
6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz
clock output.
19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz
clock output.
Table 15 - Core PLL Control Register (R/W)
Table 14 - Clock Disable Register 2 (R/W)
Zarlink Semiconductor Inc.
ZL30407
Functional Description
Functional Description
30
Data Sheet
Default
Default
00000
000
0
0
0
0
0
0
0
0