zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 18

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

3.4.2.1
The Reset State must be entered when ZL30407 is powered-up. In this state, all arithmetic calculations are halted,
clocks are stopped, the microprocessor port is disabled and all internal registers are reset to their default values.
The Reset state is entered by pulling the RESET pin low for a minimum of P1 s. When the RESET pin is pulled back
high, internal logic starts a 625 Ps initialization process before switching into the Free-run state (MS2, MS1 = 10).
3.4.2.2
The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this
occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. In
the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30407
Master Crystal Oscillator. When equipment is installed for the first time (or periodically maintained) the accuracy of
the Free-run clocks can be adjusted to within 1x10
Calibration Register.
3.4.2.3
The Normal State is entered when a good quality reference clock from the network is available for synchronization.
The ZL30407 automatically detects the frequency of the reference clock (8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz) and sets the LOCK status bit and pin high after acquiring synchronization. In the Normal state all
generated clocks (C1.5o, C2o, C4o, C6o, C8o, C16o, C19o, C34/C44 and C155) and frame pulses (F0o, F8o,
F16o) are derived from network timing. To guarantee uninterrupted synchronization, the ZL30407 has two
Acquisition PLLs that continuously monitor the quality of the incoming reference clocks. This dual architecture
enables quick replacement of a poor or failed reference and minimizes the time spent in other states.
Notes:
{AUTO} - Automatic internal transition
{MANUAL} - User initiated transition
--> - External transition
RESET = 1
RESET
Reset State
Free-Run State (Free-Run mode)
Normal State (Normal Mode or Locked Mode)
unconditional return from
MS2,MS1 = 10 forces
any state to Free-run
Figure 5 - ZL30407 State Machine in Software Control configuration
FREE-
RUN
10
MS2,MS1 = 00
MS2,MS1 = 01
OR
MS2,MS1 = 01 OR
RefSel change
HOLD-
OVER
01
Zarlink Semiconductor Inc.
MS2,MS1 = 00
Ref: OK AND
{AUTO}
-12
ZL30407
MS2,MS1
STATE
by setting the offset frequency in the Master Clock Frequency
18
RefSel Change
MS2,MS1 = 01
NORMAL
00
OR
Ref: OK-->FAIL AND
MS2,MS1 = 00
{AUTO}
HOLD-
OVER
AUTO
Ref: FAIL-->OK AND
MS2,MS1 = 00 AND
AHRD = 0
{AUTO}
Ref: FAIL-->OK AND
MS2,MS1 = 00 AND
AHRD = 1 AND MHR = 1
{MANUAL}
AHRD = 1 AND
MHR = 0
OR
Data Sheet