zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 20

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

3.4.3
In a typical Network Element application, the ZL30407 will most of the time operate in Normal mode (MS2, MS1 ==
00) generating synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs
of degraded quality and output status information for further processing. The status information from the Acquisition
PLLs and the CORE PLL combined with status information from line interfaces and framers (as listed below) forms
the basis for creating reliable network synchronization.
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The ZL30407 State Machine is designed to perform some transitions automatically, leaving other less time
dependent tasks to the control processor. The state machine includes two stimulus signals which are critical to
automatic operation: “OK --> FAIL” and “FAIL --> OK” that represent loss (and recovery) of reference signal or its
drift by more than ±30000 ppm. Both of them force the Core PLL to transition into and out of the Auto Holdover
state. In case when the reference clock on the PRI (or SEC) input is externally selected from multiple clock sources
with different frequencies then the Acquisition PLL will automatically detect this change as a reference clock failure.
In response, the Acquisition PLL will force Core PLL into Auto-Holdover state until the frequency of a new reference
is determined. This process may take up to 35 ms after which a normal locking procedure will be initiated.
The ZL30407 State Machine is controlled by the mode select pins or bits MS2, MS1. In order to avoid network
synchronization problems, the State Machine has built-in basic protection that does not allow switching the Core
PLL into a state where it cannot operate correctly e.g., it is not possible to force the Core PLL into Normal mode
when all references are lost.
3.5
In an ordinary timing generation module, the Free-run mode accuracy of generated clocks is determined by the
accuracy of the Master Crystal Oscillator. If the Master Crystal Oscillator has a manufacturing tolerance of
r4.6 ppm, the generated clocks will have no better accuracy.
The ZL30407 eliminates Crystal Oscillator tolerance problem by providing a programmable Master Clock
Frequency Calibration circuit, which can reduce oscillator manufacturing tolerance to near zero. However this
feature does not eliminate oscillator frequency drift. The value stored in the Master Clock Calibration Register can
be periodically updated to compensate for oscillator frequency drift due to ageing or due to temperature effects. The
compensation value for the Master Clock Calibration Register (MCFC3 to MCFC0) can be calculated from the
following equation:
The f
and powered long enough for the Master Crystal Oscillator to reach a steady operating temperature. Section 5.3 on
page 40 provides two examples of how to calculate an offset frequency and convert the decimal value to a binary
format. The maximum frequency compensation range of the MCFC register is equal to r 2384 ppm (r47680 Hz).
Changes to the Master Clock Calibration Register cause immediate changes in the frequency of the output clocks.
Care should be taken to ensure that changes to the Master Clock Calibration Register are made in small
increments so the frequency steps can be tolerated by downstream equipment. A rate of frequency change below
2.9 ppm/sec is suggested.
All memory in the ZL30407 is volatile; so any settings of the Master Clock Calibration Register need to be reloaded
after each RESET.
Acquisition PLLs (PRIOR, SECOR, PAH, PAFL, SAH, SAFL)
Core PLL (LOCK, HOLDOVER, FLIM)
Line interfaces (e.g. LOS - Loss of Signal, AIS - Alarm Indication Signal)
Framers (e.g. LOF - Loss of frame or Synchronization Status Messages carried over SONET S1 byte or
ESF-DS1 Facility Data Link).
m
Master Clock Frequency Calibration Circuit
frequency should only be measured after the Master Crystal Oscillator has been mounted inside a system
State Transitions
MCFC = 45036 * (-f
offset
) where:
Zarlink Semiconductor Inc.
ZL30407
20
f
offset
= f
m
- 20 000 000 Hz
Data Sheet