zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 13

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram".
3.2.1
The DCO is an arithmetic unit that continuously generates a stream of numbers that represent the phase-locked
clock. These numbers are passed to the Clock Synthesizer (see section 3.3) where they are converted into
electrical clock signals of various frequencies
3.2.2
In Normal mode, the clock generated by the DCO is phase-locked to the input reference signal and band-limited to
meet network synchronization standards. The ZL30407 provides four software programmable (FCS bit in Control
Reg 1 and FCS2 bit in Control Reg 3) and two hardware selectable (FCS pin) filtering options. The filtering
characteristics are similar to a first order low pass filter with corner frequencies that support international standards:
FCS2
(bit)
0
0
1
1
Digitally Controlled Oscillator (DCO)
Filters
(pin/bit)
FCS
0
1
0
1
MUX
HOLDOVER
1.5 Hz
0.1 Hz
12 Hz
Filter
6 Hz
RefAlign
LOCK
Meets requirements of G.813 Option 1 and GR-1244 stratum 3 clocks.The
maximum phase slope is limited to 41 ns in 1.326 ms.
Meets requirements of G.813 Option 2, GR-253 for SONET stratum 3 and
GR-253 for SONET Minimum Clocks (SMC).The maximum phase slope is
limited to 885 ns in one second.
There is no phase slope limiter active in this application.
Meets requirements of G.813 Option 1 for SDH Equipment Clocks (SEC) and
GR-1244 for Stratum 4 and Stratum 4E clocks. The maximum phase slope is
limited to 50 ns in 1.326 ms.
Figure 3 - Core PLL Functional Block Diagram
Detector
Phase
FSM
Table 1 - Loop Filter Selection
Zarlink Semiconductor Inc.
ZL30407
13
FCS
Filters
(Control bit only)
FCS2
Conformance
DCO
Data Sheet