zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 7

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Pin Description
Pin #
2-5
7-8
10
11
12
13
14
15
16
17
18
19
1
6
9
A1-A4
A5-A6
Name
C16o
F16o
GND
GND
VDD
MS1
MS2
FCS
C8o
C4o
C2o
F0o
IC
Internal Connection. Leave unconnected.
Address 1 to 4 (5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Ground. Negative power supply.
Address 5 to 6 (5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Filter Characteristic Select (Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30407. Set this pin high to have a loop filter
corner frequency of 0.1 Hz and limit the phase slope to 885 ns/sec. Set this pin
low to have corner frequency of 1.5 Hz and limit the phase slope to 41 ns per
1.326 ms. Connect to ground in Software Control. This pin is internally pulled
down to GND.
Positive Power Supply
Ground
Frame Pulse ST-BUS 8.192 Mbps (CMOS tristate output). This is an 8 kHz,
61 ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mbps.
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
Frame Pulse ST-BUS 2.048 Mbps (CMOS tristate output). This is an 8 kHz,
244 ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mbps and
4.096 Mbps.
Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30407 mode of
operation (Normal, Holdover or Free-run), see Table 2 on page 22 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30407 mode of
operation (Normal, Holdover or Free-run), see Table 2 on page 22 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
Zarlink Semiconductor Inc.
ZL30407
7
Description
Data Sheet