zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 9

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RefAlign
PRIOR
RefSel
Name
C1.5o
C19o
GND
Tms
C6o
Tdo
Tclk
Trst
NC
NC
Tdi
IC
IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on
this pin on the falling edge of Tclk clock. If not used, this pin should be left
unconnected.
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG
test logic. If not used, this pin should be pulled up to VDD.
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG
TAP controller. This pin should be pulsed low on power-up to ensure that the
device is in the normal functional state. This pin is internally pulled up to VDD.
If this pin is not used then it should be connected to GND.
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test
instructions and data. This pin is internally pulled up to VDD. If not used, this
pin should be left unconnected.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Primary Reference Out of Range (Output). Logic high at this pin indicates
that the Primary Reference is off the PLL centre frequency by more than
r12ppm. These thresholds support Stratum 3 applications. See PRIOR bit
description in Status Register 1 for details.
Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz
DS1 rate clock.
Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz
DS2 rate clock.
Internal Connection. Connect this pin to Ground.
Ground
Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz
clock.
Reference Source Select (Input). A logic low selects the PRI (primary)
reference source as the input reference signal and logic high selects the SEC
(secondary) input. The logic level at this input is sampled at the rising edge of
F8o. This pin is internally pulled down to GND.
Reference Alignment (Input). In Hardware Control pulling this pin low for
250 Ps initiates phase realignment between the input reference and the
generated output clocks. This pin should never be tied low permanently.
Please see Section 3.2.5, Reference Alignment (RefAlign) for more
information. Internally this pin is pulled down to GND.
Zarlink Semiconductor Inc.
ZL30407
9
Description
Data Sheet