zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 8

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
20
21
22
23
24
25
26
27
28
29
30
31
32
33
E3DS3/OC3
E3/DS3
C155N
C155P
Name
AVDD
GND
GND
GND
SEC
VDD
F8o
PRI
NC
IC
Frame Pulse ST-BUS/GCI 8.192 Mbps (CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mbps. See Figure 18 for details.
E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks. In Software Control connect this pin to ground.
E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock. Connect this input to ground in Software
Control.
Secondary Reference (Input). This input is used as a secondary reference
source for synchronization. The ZL30407 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44
MHz clock. In Hardware Control, selection of the input reference is based upon
the RefSel control input. This pin is internally pulled up to VDD.
Primary Reference (Input). This input is used as a primary reference source
for synchronization. The ZL30407 can synchronize to the falling edge of the 8
kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
Ground
Internal Connection. Leave unconnected.
Ground
Positive Analog Power Supply. Connect this pin to VDD.
Positive Power Supply
Clock 155.52 MHz (LVDS output). Differential outputs for the 155.52 MHz
clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or
they can be disabled by applying logic high. In the disabled state the LVDS
outputs are internally terminated with an integrated 100: resistor (two 50:
resistors connected in series). The middle point of these resistors is internally
biased from a 1.25 V LVDS bias source.
Ground
No internal bonding Connection. Leave unconnected.
Zarlink Semiconductor Inc.
ZL30407
8
Description
Data Sheet