zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet - Page 16

• Manufacturer Part Number: zl30407qcc
• Description: Sonet/sdh Network Element Pll
• Manufacturer: Zarlink Semiconductor

3. For 6 Hz and 12 Hz filtering applications (FCS = 1, FCS2 = 1 or FCS = 0, FCS2 = 1)
After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks
to remove the static phase error. The PLL will then begin the normal locking procedure. The LOCK pin will remain
high during the realignment process.
3.3
The output of the Core PLL is connected to the Clock Synthesizer that generates twelve clocks and three frame
pulses.
3.3.1
The ZL30407 provides the following clocks (see Figure 18 "ST-BUS and GCI Output Timing", Figure 19 "DS1 and
DS2 Clock Timing", Figure 20 "C155o and C19o Timing", and Figure 23 "E3 and DS3 Output Timing" for details):
The ZL30407 provides the following frame pulses (see Figure 18 "ST-BUS and GCI Output Timing" for details). All
frame pulses have the same 125 Ps period (8kHz frequency):
The combination of two pins, E3DS3/OC3 and E3/DS3, controls the selection of different clock configurations.
When the E3DS3/OC3 pin is high then the C155o (155.52 MHz) clock is disabled and the C34/44 clock is output at
its nominal frequency. The logic level on the E3/DS3 input determines if the output clock on the C34/44 output is
34.368 MHz (E3) or 44.736 MHz (DS3) (see Figure 4, “C34/C44, C155o Clock Generation Options,” on page 17 for
details).
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Wait until the ZL30407 LOCK indication is high, indicating that it is locked
Pull RefAlign low
Hold RefAlign low for 3 sec
Pull RefAlign high
Clock Synthesizer
C1.5o
C2o
C4o
C6o
C8o
C8.5o
C11o
C16o
C19o
C34o
C44o
C155
F0o : 244 ns wide, logic low frame pulse
F8o : 122 ns wide, logic high frame pulse
F16o : 61 ns wide, logic low frame pulse
Output Clocks
: 1.544 MHz clock with nominal 50% duty cycle
: 2.048 MHz clock with nominal 50% duty cycle
: 4.096 MHz clock with nominal 50% duty cycle
: 6.312 MHz clock with nominal 50% duty cycle
: 8.192 MHz clock with nominal 50% duty cycle
: 8.592 MHz clock with duty cycle from 30 to 70%.
: 11.184 MHz clock with duty cycle from 30 to 70%.
: 16.384 MHz clock with nominal 50% duty cycle
: 19.44 MHz clock with nominal 50% duty cycle
: 34.368 MHz clock with nominal 50% duty cycle
: 44.736 MHz clock with nominal 50% duty cycle
: 155.52 MHz clock with nominal 50% duty cycle.
Zarlink Semiconductor Inc.
ZL30407
16
Data Sheet