C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 159

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ECP1R
R/W
Bit7
ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt.
This bit sets the masking of the CP1 rising edge interrupt.
0: Disable CP1 rising edge interrupts.
1: Enable CP1 rising edge interrupts.
ECP1F: Enable Comparator1 (CP1) Falling Edge Interrupt.
This bit sets the masking of the CP1 falling edge interrupt.
0: Disable CP1 falling edge interrupts.
1: Enable CP1 falling edge interrupts.
ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable CP0 rising edge interrupts.
ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable CP0 falling edge interrupts.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable PCA0 interrupts.
1: Enable PCA0 interrupts.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable ADC0 Window Comparison Interrupt.
ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable SMBus interrupts.
1: Enable SMBus interrupts.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable SPI0 interrupts.
1: Enable SPI0 interrupts.
ECP1F
R/W
SFR Definition 11.14. EIE1: Extended Interrupt Enable 1
Bit6
ECP0R
R/W
Bit5
ECP0F
R/W
Bit4
Rev. 1.4
EPCA0
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
EWADC0
R/W
Bit2
C8051F130/1/2/3
ESMB0
R/W
Bit1
SFR Address:
SFR Page:
ESPI0
R/W
Bit0
0xE6
All Pages
00000000
Reset Value
159