C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 315

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

Bits 7–0: TL0: Timer 0 Low Byte.
Bits7–5: UNUSED. Read = 000b, Write = don’t care.
Bit4:
Bit3:
Bit2:
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits
R/W
R/W
Bit7
Bit7
-
The TL0 register is the low byte of the 16-bit Timer 0.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
UNUSED. Read = 0b, Write = don’t care.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
*Note: External clock divided by 8 is synchronized with the system
SCA1
R/W
R/W
Bit6
Bit6
0
0
1
1
-
clock, and external clock must be less than or equal to the
system clock frequency to operate the timer in this mode.
SFR Definition 23.3. CKCON: Clock Control
SFR Definition 23.4. TL0: Timer 0 Low Byte
SCA0
R/W
R/W
Bit5
Bit5
-
0
1
0
1
T1M
R/W
R/W
Bit4
Bit4
External clock divided by 8*
System clock divided by 12
System clock divided by 48
System clock divided by 4
Prescaled Clock
Rev. 1.4
T0M
R/W
Bit3
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
R/W
Bit2
R/W
Bit2
-
C8051F130/1/2/3
SCA1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SCA0
R/W
R/W
Bit0
Bit0
0x8A
0
0x8E
0
00000000
Reset Value
00000000
Reset Value
315