C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 34

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.8.
All devices include either a 12 or 10-bit SAR ADC (ADC0) with a 9-channel input multiplexer and program-
mable gain amplifier. With a maximum throughput of 100 ksps, the 12 and 10-bit ADCs offer true 12-bit lin-
earity with an INL of ±1LSB. The ADC0 voltage reference can be selected from an external VREF pin, or
(on the C8051F12x devices) the DAC0 output. On the 100-pin TQFP devices, ADC0 has its own dedicated
Voltage Reference input pin; on the 64-pin TQFP devices, the ADC0 shares a Voltage Reference input pin
with the 8-bit ADC2. The on-chip voltage reference may generate the voltage reference for other system
components or the on-chip ADCs via the VREF output pin.
The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers.
One input channel is tied to an internal temperature sensor, while the other eight channels are available
externally. Each pair of the eight external input channels can be configured as either two single-ended
inputs or a single differential input. The system controller can also put the ADC into shutdown mode to
save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to
16 in powers of 2. The gain stage can be especially useful when different ADC input channels have widely
varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in dif-
ferential mode, a DAC could be used to provide the DC offset).
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. Conversion completions are indicated by a
status bit and an interrupt (if enabled). The resulting 10 or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data
is within or outside of a specified range. The ADC can monitor a key voltage continuously in background
mode, but not interrupt the controller unless the converted data is within the specified window.
34
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
12 or 10-Bit Analog to Digital Converter
Analog Multiplexer
AGND
SENSOR
TEMP
+
+
+
+
-
-
-
-
AMUX
(SE or
9-to-1
DIFF)
Figure 1.13. 12-Bit ADC Block Diagram
Programmable Gain
X
Amplifier
Configuration, Control, and Data
External VREF
+
-
DAC0 Output
AV+
Rev. 1.4
Registers
Pin
ADC
VREF
12-Bit
SAR
Start
Conversion
Window Compare
12
Logic
Write to AD0BUSY
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
ADC Data
Registers
Conversion
Complete
Compare
Interrupt
Interrupt
Window