C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 217
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
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Bit 7:
Bits 6–0: CHMSCTH: Cache Miss Penalty Accumulator (bits 11–5)
Bit 7–1:
Bit 0:
CHMSOV
Bit7
Bit7
R
R
-
CHMSOV: Cache Miss Penalty Overflow.
This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was
last written.
0: The Cache Miss Penalty Accumulator has not overflowed since it was last written.
1: An overflow of the Cache Miss Penalty Accumulator has occurred since it was last written.
These are bits 11-5 of the Cache Miss Penalty Accumulator. The next four bits (bits 4-1) are
stored in CHMSCTL in the CCH0TN register.
The Cache Miss Penalty Accumulator is incremented every clock cycle that the processor is
delayed due to a cache miss. This is primarily used as a diagnostic feature, when optimizing
code for execution speed.
Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator.
Reading from CHMSCTH returns the current value of CHMSTCH, and latches bits 4-1 into
CHMSTCL so that they can be read. Because bit 0 of the Cache Miss Penalty Accumulator
is not available, the Cumulative Miss Penalty is equal to 2 * (CCHMSTCH:CCHMSTCL).
Reserved.
FLBUSY: Flash Busy
This bit indicates when a Flash write or erase operation is in progress.
0: Flash is idle or reading.
1: Flash write/erase operation is currently in progress.
SFR Definition 16.4. CCH0MA: Cache Miss Accumulator
R/W
R/W
Bit6
Bit6
-
SFR Definition 16.5. FLSTAT: Flash Status
R/W
R/W
Bit5
Bit5
-
R/W
R/W
Bit4
Bit4
-
CHMSCTH
Rev. 1.4
R/W
R/W
Bit3
Bit3
-
C8051F120/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
-
C8051F130/1/2/3
R/W
R/W
Bit1
Bit1
-
SFR Address:
SFR Address:
FLBUSY 00000000
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
0x9A
F
0x88
F
00000000
Addressable
Reset Value
Reset Value
Bit
217
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