ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 100

• Manufacturer Part Number: ATMEGA406-1AAU
• Description: IC AVR MCU 40K 1MHZ 48LQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA406-1AAU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: I²C
• Peripherals: POR, WDT
• Number Of I /o: 18
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 30 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 1MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (max): 25V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 10-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -30C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 18
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 2KB
• Cpu Speed: 1MHz
• Rohs Compliant: Yes
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5.1
16.5.2
16.6
16.6.1
100
16-bit Timer/Counter Register Description
ATmega406
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
TCCR1B – Timer/Counter1 Control Register B
Figure 16-3
bit names indicates the device number (n = 1 for Timer/Counter1), and the “x” indicates output
compare unit (A). The elements of the block diagram that are not directly a part of the output
compare unit are gray shaded.
Figure 16-3. Output Compare Unit, Block Diagram
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the output compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed.
• Bit 7:4 – Res: Reserved Bits
These bits is a reserved bit in the ATmega406 and always reads as zero.
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to 0x00 in the CPU clock cycle
after a compare match.
Bit
(0x81)
Read/Write
Initial Value
shows a block diagram of the output compare unit. The small “n” in the register and
R/W
7
–
0
R/W
6
–
0
OCRnxH (8-bit)
TEMP (8-bit)
OCRnx (16-bit Register)
R
5
–
0
OCRnxL (8-bit)
DATA BUS
R/W
4
–
0
=
(16-bit Comparator )
CTC1
(8-bit)
R/W
3
0
TCNTnH (8-bit)
OCFnx (Int.Req.)
CS12
R/W
TCNTn (16-bit Counter)
2
0
CS11
R/W
TCNTnL (8-bit)
1
0
CS10
R/W
0
0
2548E–AVR–07/06
TCCR1B