ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 170

• Manufacturer Part Number: ATMEGA406-1AAU
• Description: IC AVR MCU 40K 1MHZ 48LQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA406-1AAU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: I²C
• Peripherals: POR, WDT
• Number Of I /o: 18
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 30 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 1MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (max): 25V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 10-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -30C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 18
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 2KB
• Cpu Speed: 1MHz
• Rohs Compliant: Yes
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

170
ATmega406
Connect/Disconnect Interrupt is executed. If both SDA and SCL are high during reset, TWBCIF
will be set after reset. Otherwise TWBCIF will be cleared after reset.
• Bit 6 - TWBCIE: TWI Bus Connect/Disconnect Interrupt Enable
When the TWBCIE bit and the I-bit in the Status Register are set, the TWI Bus Connect/Discon-
ne ct In terr upt is e nab le d. Th e corre spon ding inte rrup t is execu ted if a TWI Bus
Connect/Disconnect occurs, i.e., when the TWBCIE bit is set.
• Bit 5:3 - Res: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 2:1 - TWBDT1, TWBDT0: TWI Bus Disconnect Time-out Period
The TWBDT bits decides how long both the TWI data (SDA) and clock (SCL) signals must be
low before generating the TWI Bus Disconnect Interrupt. The different configuration values and
their corresponding time-out periods are shown in
Table 25-8.
• Bit 0 - TWBCIP: TWI Bus Connect/Disconnect Interrupt Polarity
The TWBCIP bit decide if the TWI Bus Connect/Disconnect Interrupt Flag (TWBCIF) should be
set on a Bus Connect or a Bus Disconnect. If TWBCIP is cleared, the TWBCIF flag is set on a
Bus Connect. If TWBCIP is set, the TWBCIF flag is set on a Bus Disconnect.
TWBDT1
0
0
1
1
TW Bus Disconnect Time-out Period
TWBDT0
0
1
0
1
TWI Bus Disconnect Time-out Period
250 ms
500 ms
1000 ms
2000 ms
Table
25-8.
2548E–AVR–07/06