ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 95

• Manufacturer Part Number: ATMEGA406-1AAU
• Description: IC AVR MCU 40K 1MHZ 48LQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA406-1AAU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: I²C
• Peripherals: POR, WDT
• Number Of I /o: 18
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 30 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 1MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (max): 25V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 10-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -30C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 18
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 2KB
• Cpu Speed: 1MHz
• Rohs Compliant: Yes
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. 16-bit Timer/Counter1
16.1
16.1.1
2548E–AVR–07/06
Overview
Registers
The 16-bit Timer/Counter unit allows accurate program execution timing (event management).
The main features are:
•
•
•
Most register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the output compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. The physical I/O reg-
ister and bit locations for ATmega406 are listed in the
Description” on page
A simplified block diagram of the 16-bit Timer/Counter is shown in
I/O registers, including I/O bits and I/O pins, are shown in bold.
The PRTIM1 bit in
enable TImer/Counter1 module.
Figure 16-1. 16-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT1) and the Output Compare Register (OCR1A) are both 16-bit regis-
ters. Special procedures must be followed when accessing the 16-bit registers. These
procedures are described in the section
Timer/Counter Control Register (TCCR1B) is an 8-bit register an has no CPU access restric-
tions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are visible in the Timer
Interrupt Flag Register (TIFR). Both interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter is clocked internally via the prescaler. The Clock Select logic block controls
which clock source the Timer/Counter uses to increment its value. The Timer/Counter is inactive
when no clock source is selected. The output from the clock select logic is referred to as the
timer clock (clk
One Output Compare Unit
Clear Timer on Compare Match (Auto Reload)
Two Independent Interrupt Sources (TOV1 and OCF1A)
T
1
).
”PRR0 – Power Reduction Register 0” on page 36
100.
Timer/Counter
OCRnA
TCNTn
=
Count
Clear
”Accessing 16-bit Registers” on page
Control Logic
=0xFFFF
TCCRnB
clk
Tn
”16-bit Timer/Counter Register
Figure
TOVn
(Int.Req.)
OCFnA
(Int.Req.)
must be written to zero to
ATmega406
16-1. CPU accessible
96.The
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