AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 158

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

All parameters needed to configure PLL and the divider are located in the CKGR_PLLR
register.
The DIV field is used to control divider itself. A value between 0 and 255 can be programmed.
Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0
which means that divider is turned off.
The OUT field is used to select the PLL B output frequency range.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the
PMC_SR register after CKGR_PLLR register has been written.
Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set
in the PMC_SR register. This can be done either by polling the status register or by waiting
the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the
PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single write
operation. If at some stage one of the following parameters, MUL, DIV is modified, LOCK bit
will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again.
The user is constrained to wait for LOCK bit to be set before using the PLL output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the
USB clock(s).
Code Example:
write_register(CKGR_PLLR,0x00040805)
If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL
input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after
eight slow clock cycles.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is slow clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to slow clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by polling the status register or by
waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been
enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred
programming sequence for the PMC_MCKR register is as follows:
AT91SAM7A3 Preliminary
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6042E–ATARM–14-Dec-06