AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 260

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

WD
WD
WD
Figure 28-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 28-6. Master Write with One Byte Internal Address and Multiple Data Bytes
Figure 28-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
260
TXCOMP
TWD
TWD
TWD
TXRDY
Three bytes internal address
Two bytes internal address
One byte internal address
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
S
S
S
AT91SAM7A3 Preliminary
S
Write THR
Write THR
DADR
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the
other status bits, an interrupt can be generated if enabled in the interrupt enable register
(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the
control register starts the transmission. The data is shifted in the internal shifter and when an
acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see
6
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY
bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a
slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the
other slave address bits in the internal address register (TWI_IADR).
W
W
W
W
below). The master generates a stop condition to end the transfer.
A
A
A
A
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
IADR(23:16)
IADR(15:8)
IADR(7:0)
IADR(7:0)
A
A
A
A
A
A
A
IADR(15:8)
IADR(7:0)
S
DADR
IADR(15:8)
DATA
IADR(7:0)
DATA
A
A
R
Write THR
A
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
DATA
R
S
Write THR
A
A
A
A
N
DADR
DATA
P
P
DATA
DATA
DATA
6042E–ATARM–14-Dec-06
R
N
P
A
N
A
Figure 28-
A
P
P
P