AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 577

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40.2.8
40.2.8.1
40.2.8.2
40.2.8.3
6042E–ATARM–14-Dec-06
Two-wire Interface (TWI)
TWI: Clock Divider
TWI: Possible Receive Holding Register Corruption
TWI: NACK Status Bit Lost
the data start and one data bit is lost. This problem does not exist when generating a periodic
synchro.
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are AT91SAM7A3 signals, TXD is the delayed
data to connect to the device.
The value of CLDIV x 2
be less than or equal to 8191⋅
None.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
AT91SAM7A3 Preliminary
CKDIV
must
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