AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 506

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.5.1
Figure 36-8. Enabling Low-power Mode
36.6.5.2
6042E–ATARM–14-Dec-06
(CAN_MSR3)
(CAN_MSR1)
(CAN_MR)
(CAN_SR)
(CAN_SR)
CAN BUS
WAKEUP
CAN_TIM
SLEEP
MRDY
MRDY
LPM
Enabling Low-power Mode
Disabling Low-power Mode
LPEN= 1
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A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR
global register. The CAN controller enters Low-power Mode once all pending transmit mes-
sages are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register
is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is gener-
ated while SLEEP is set.
The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The
WAKEUP signal is automatically cleared once SLEEP is set.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is impor-
tant to note that those messages with higher priority than the last message transmitted can be
received between the LPM command and entry in Low-power Mode.
Once in Low-power Mode, the CAN controller clock can be switched off by programming the
chip’s Power Management Controller (PMC). The CAN controller drains only the static current.
Error counters are disabled while the SLEEP signal is set to one.
Thus, to enter Low-power Mode, the software application must:
Now the CAN Controller clock can be disabled. This is done by programming the Power Man-
agement Controller (PMC).
The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is
done by an external module that may be embedded in the chip. When it is notified of a CAN
bus activity, the software application disables Low-power Mode by programming the CAN
controller.
– Set LPM field in the CAN_MR register
– Wait for SLEEP signal rising
Arbitration lost
AT91SAM7A3 Preliminary
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