AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 591

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6042E–ATARM–14-Dec-06
Version
6042E
Comments
Section 4.1, ”100-lead LQFP Package Outline”
Outline (Top View)”
Peripheral and System Controller Memory Maps consolidated in
Table 11-1, “Peripheral Identifiers,” on page
Table 3-1, “Signal Description,” on page
Figure 8-2, ”Internal Memory Mapping”
Debug and Test:
RSTC:
RTT: Added note to
WDT: WV changed to WDV in
and the 6th and 7th paragraph rewritten on
PDC:
AIC:
PMC:Section 23.3.1, ”Main Oscillator
Added a note defining PIDx to
”PMC Peripheral Clock Disable Register”
DBGU:Section 25.5.10, ”Debug Unit Chip ID Register”
on page
Figure 25-1, ”Debug Unit Functional Block
“Power-on Reset”.
PIO:
SPI:
Section 27.6.3, ”Master Mode
Section 27.7.1, ”SPI Control
on page
Section 27.7.9, ”SPI Chip Select
Transfers” on page
Section 27.6.3.8, ”Mode Fault
TWI:
Status and Interrupt register tables.
Figure 27-9, ”Slave Mode Functional Block
”Register Mapping” on page
Figure 26-3, ”I/O Line Control Logic”
Section 28.6, ”Two-wire Interface (TWI) User Interface”
Section 21.1,
Section 14.3.1, ”Reset Controller
203.
245.
Section 13.6.3, ”Debug Unit”
256.
”Overview”, user interface description updated.
replaced.
Section 15.3, ”Functional Description”
Register”, added information to bit description
Operations”, update to SPI_RDR information
Detection”, updated.
Section 17.2, ”Block Diagram”
Section 24.9.4, ”PMC Peripheral Clock Enable
Register”, corrected equation in
140, footnote
Connections”, updated.
reference to boot memory removed.
5, SHDW and FWUP, comments updated
Overview”, updated with crystal oscillator effect on startup counter. 3005
and
updated,
Diagram”, “ice_nreset” signal name replaced by pad name
page 78
29, SYSIRQ changed to SYSC.
Section 24.9.6, ”PMC Peripheral Clock Status Register”
Debug Unit Chip ID value is 0x260A0941
replaces Mechanical Overview,
(2)
Diagram”, FLOAD removed.
added in reference to PID2...PID31 bit fields.
beginning with “To prevent a software deadlock
update to the table in
UNRE and OVRE bit fields removed from TWI
and in
Figure 8-1 on page
”DLYBCT: Delay Between Consecutive
Section 17.3, ”Functional
AT91SAM7A3 Preliminary
”SWRST: SPI Software Reset”
”ARCH: Architecture Identifier”
Register”,
Figure 4-1, ”100-lead LQFP
16.
Section 24.9.5,
Description”,
Change
Request
Ref.
3180
rfo
rfo
2522
3002
2548
3282
2468
1744/05-459
2832
3053
1542
1543
1676
2470
xi