AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 395

IC ARM7 MCU FLASH 256K 100LQFP

AT91SAM7A3-AU

Manufacturer Part Number
AT91SAM7A3-AU
Description
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7A3-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, MMC, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
AT91SAM7xx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/SPI/I2S/TWI/USART/USB
On-chip Adc
2(8-chx10-bit)
Number Of Timers
3
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
Minimum Operating Temperature
- 40 C
Cpu Family
91S
Device Core Size
32b
Frequency (max)
60MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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6042E–ATARM–14-Dec-06
Figure 32-4. Non Overlapped Center Aligned Waveforms
Note:
When center aligned, the internal channel counter increases up to CPRD and.decreases down
to 0. This ends the period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends
the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for
a left aligned channel.
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low
• the waveform alignment. The output waveform can be left or center aligned. Center
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
becomes, respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
level. This property is defined in the CPOL field of the PWM_CMRx register. By default the
signal starts by a low level.
aligned waveforms can be used to generate non overlapped waveforms. This property is
defined in the CALG field of the PWM_CMRx register. The default mode is left aligned.
PWM0
PWM1
(
---------------------------------------- -
(
--------------------------------------------------- -
2
2
duty cycle
×
×
duty cycle
X CPRD
CPRD DIVA
MCK
1. See
×
MCK
×
No overlap
Figure 32-5 on page 397
=
)
=
(
------------------------------------------------------------------------------------------------------- -
(
---------------------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
)
(
period 2 ⁄
or
Period
(
--------------------------------------------------- -
2 CPRD
×
) 1 fchannel_x_clock
MCK
period
×
(
DIVB
period 2 ⁄
for a detailed description of center aligned waveforms.
)
AT91SAM7A3 Preliminary
)
×
CDTY
×
CDTY
)
) )
395

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