MC908AP64CFAE Freescale Semiconductor, MC908AP64CFAE Datasheet - Page 162

• Manufacturer Part Number: MC908AP64CFAE
• Description: IC MCU 64K 8MHZ SPI 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP64CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• Package: 48LQFP
• Family Name: HC08
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Serial Communications Interface Module (SCI)
11.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following
times (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 11-2
162
•
•
RT CLOCK
RT CLOCK
SAMPLES
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
CLOCK
RESET
STATE
RxD
Figure
RT
summarizes the results of the start bit verification samples.
11-6):
RT3, RT5, and RT7
QUALIFICATION
Samples
START BIT
Figure 11-6. Receiver Data Sampling
000
001
010
011
100
101
110
111
MC68HC908AP Family Data Sheet, Rev. 4
Table 11-2. Start Bit Verification
VERIFICATION
START BIT
Verification
Start Bit
Yes
Yes
Yes
Yes
No
No
No
No
START BIT
SAMPLING
DATA
Noise Flag
0
1
1
0
1
0
0
0
Freescale Semiconductor
LSB