MC908AP64CFAE Freescale Semiconductor, MC908AP64CFAE Datasheet - Page 242

IC MCU 64K 8MHZ SPI 48-LQFP

MC908AP64CFAE

Manufacturer Part Number
MC908AP64CFAE
Description
IC MCU 64K 8MHZ SPI 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC908AP64CFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
Package
48LQFP
Family Name
HC08
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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Price
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Multi-Master IIC Interface (MMIIC)
14.6.7 MMIIC CRC Data Register (MMCRCDR)
When the MMIIC module is enabled, MMEN = 1, and the CRC buffer full flag is set (MMCRCBF = 1), data
in this read-only register contains the generated CRC byte for the last byte of received or transmitted data.
A CRC byte is generated for each received and transmitted data byte and loaded to the CRC data
register. The MMCRCBF bit will be set to indicate the CRC byte is ready in the CRC data register.
Reading the CRC data register clears the MMCRCBF bit. If the CRC data register is not read, the
MMCRCBF bit will be cleared by hardware before the next CRC byte is loaded.
14.6.8 MMIIC Frequency Divider Register (MMFDR)
The three bits in the frequency divider register (MMFDR) selects the divider to divide the bus clock to the
desired baud rate for the MMIIC data transfer.
Table 14-2
240
shows the divider values for MMBR[2:0].
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 14-11. MMIIC Frequency Divider Register (MMFDR)
MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
$004E
$004F
Bit 7
Bit 7
Figure 14-10. MMIIC CRC Data Register (MMCRCDR)
0
0
0
= Unimplemented
= Unimplemented
6
0
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
5
0
0
4
0
4
0
0
3
0
3
0
0
MMBR2
2
0
2
1
MMBR1
1
0
1
0
Freescale Semiconductor
MMBR0
Bit 0
Bit 0
0
0

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