MC908AP64CFAE Freescale Semiconductor, MC908AP64CFAE Datasheet - Page 252

• Manufacturer Part Number: MC908AP64CFAE
• Description: IC MCU 64K 8MHZ SPI 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP64CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• Package: 48LQFP
• Family Name: HC08
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Analog-to-Digital Converter (ADC)
The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The
clock source is either the bus clock or CGMXCLK and is selectable by the ADICLK bit located in the ADC
clock register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock source, with a divide-by-four
prescale, and the bus speed is set at 2MHz:
Since an ADC cycle may be comprised of several bus cycles (four in the previous example) and the start
of a conversion is initiated by a bus cycle write to the ADSCR, from zero to four additional bus cycles may
occur before the start of the initial ADC cycle. This results in a fractional ADC cycle and is represented as
the 17th cycle.
15.3.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the selected channel, filling the ADC
data register with new data after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit is set after each conversion and can be cleared by writing to the ADC status and control register
or reading of the ADRL0 data register.
15.3.5 Auto-Scan Mode
In auto-scan mode, the ADC input channel is selected by the value of the 2-bit up-counter, instead of the
channel select bits, ADCH[4:0]. The value of the counter also defines the data register ADRLx to be used
to store the conversion result. When ASCAN bit is set, a write to ADC status and control register (ADSCR)
will reset the auto-scan up-counter and ADC conversion will start on the channel 0 up to the channel
number defined by the integer value of AUTO[1:0]. After a channel conversion is completed, data is stored
in ADRLx and the COCO-bit will be set. The counter value will be incremented by 1 and a new conversion
will start. This process will continue until the counter value reaches the value of AUTO[1:0]. When this
happens, it indicates that the current channel is the last channel to be converted. Upon the completion on
the last channel, the counter value will not be incremented and no further conversion will be performed.
To start another auto-scan cycle, a write to ADSCR must be performed.
It is recommended that user should disable the auto-scan function before switching channel and also
before entering STOP mode.
250
Number of bus cycles = 16 µs × 2MHz = 32 to 34 cycles
Conversion time =
The ADC frequency must be between f
to meet A/D specifications. (See
The system only provides 8-bit data storage in auto-scan code, user must
clear MODE[1:0] bits to select 8-bit truncation mode before entering
auto-scan mode.
MC68HC908AP Family Data Sheet, Rev. 4
16 to17 ADC cycles
4MHz ÷ 4
22.5 5V DC Electrical
NOTE
NOTE
ADIC
= 16 to 17 µs
minimum and f
Characteristics.).
ADIC
maximum
Freescale Semiconductor