ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 133

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.4.4
13.5
8077H–AVR–12/09
Reading the Pin value
Wired-AND
Figure 13-6. Output configuration - Wired-OR with optional pull-down.
With Wired-AND configuration, the pin will be driven low when the corresponding bit in OUT is
written to zero. When OUT is set to one, the pin is released allowing the pin to be pulled low with
the internal or an external pull-resistor. If internal pull-up is used, this is also active if the pin is
set as input.
Figure 13-7. Output configuration - Wired-AND with optional pull-up.
Independent of the pin data direction, the pin value can be read from the IN register as shown in
Figure 13-1 on page
register bit and the preceding flip-flop constitute a synchronizer. The synchronizer is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock. The
Synchronizer introduces a delay on the internal signal line.
timing diagram of the synchronization when reading an externally applied pin value. The maxi-
mum and minimum propagation delays are denoted t
130. If the digital input is disabled, the pin value cannot be read. The IN
OUTn
OUTn
INn
INn
pd,max
and t
Figure 13-8 on page 134
pd,min
respectively.
Pn
Pn
XMEGA A
shows a
133